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MPC8540 Datasheet(PDF) 931 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 931 Page - Freescale Semiconductor, Inc

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External Signal Descriptions
MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
17-7
17.2 External Signal Descriptions
This section describes the signal names of the RapidIO block, their meanings, and the timing
relationships that exist among the signals.
17.2.1 Signals Overview
The RapidIO block implements the functionality described in the Parallel RapidIO Interconnect
Specification for an 8-bit parallel interface with separate transmit and receive ports as shown in
Figure 17-2.
Figure 17-2. RapidIO Interface Signals Model
The RapidIO signals are implemented as differential pairs of signals. Table 17-4 lists the external
RapidIO signals implemented on this interface.
Table 17-4. RapidIO Interface Signals Summary
Signal Name
Function
Pins I/O
RIO_RCLK
Port receive clock
1
I
RIO_RCLK
Port receive clock, inverted (differential pair)
1
I
RIO_RD [0:7]
Port receive data
8
I
RIO_RD [0:7]
Port receive data, inverted (differential pair)
8
I
RIO_RFRAME
Port receive framing signal
1
I
RIO_RFRAME
Port receive framing signal, inverted (differential pair)
1
I
RIO_TCLK
Port transmit clock
1
O
RIO_TCLK
Port transmit clock, inverted (differential pair)
1
O
RIO_TD[0:7]
Port transmit data
8
O
RIO_TD[0:7]
Port transmit data, inverted (differential pair)
8
O
RIO_TFRAME
Port transmit framing signal
1
O
RIO_TFRAME
Port transmit framing signal, inverted (differential pair)
1
O
RIO_TX_CLK_IN
Port transmit clock in
1
I
RIO_TX_CLK_IN
Port transmit clock in, inverted (differential pair)
1
I
8
1
1
RIO_TCLK
RIO_TD[0:7]
1
RIO_RCLK
8
RIO_RD[0:7]
1
RIO_RFRAME
RapidIO Interface
RIO_TFRAME
RIO_TX_CLK_IN



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