MPC8540 datasheet(930/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

17-6

Freescale Semiconductor

RapidIO Interface

17.1.4.3 Error Checking Disable Mode

Error checking can be enabled or disabled by setting a bit in the port control CSR. This mode

disables all RapidIO transmission error checking. Device behavior is undefined if error checking

is disabled and an error condition occurs.

17.1.4.4 Output Port Enable Mode

The output port can be disabled by setting a bit in the port control CSR. In this mode, RapidIO

does not issue any packets of its own, except in response to maintenance packets.

17.1.4.5 Output Port Driver Disable Mode

This mode, controlled by PCCSR[OPD], disables RapidIO input receivers and output drivers.

17.1.4.6 Accept All Mode

This mode is controlled by a bit (CR[AA]) in the RapidIO configuration register. While this mode

is enabled, all packets are accepted regardless of the target ID. Table 17-3 describes the behavior

with respect to the accept all mode.

17.1.4.7 Packet Response Time-Out Disable Mode

The RapidIO packet response time-out counters can be disabled by setting a bit in the RapidIO

port notification/fatal error disable register. For more information, see Section 17.3.2.3.2, “Port

Notification/Fatal Error Detect Disable Register (PNFEDiR).”

17.1.4.8 Link Response Time-Out Disable Mode

The RapidIO link time-out counters can be disabled by setting a bit in the RapidIO port

notification/fatal error disable register. For more information, see Section 17.3.2.3.2, “Port

Notification/Fatal Error Detect Disable Register (PNFEDiR).”

Table 17-2. CRC Checking Mode

PCR[CCE]

Mode

CRC checking disabled

CRC enabled with hardware-based recovery

Table 17-3. Accept All Mode Behavior

Accept All (CR[AA])

Device Behavior for Target ID

≠ Device ID

Error reported in PNFEDR[ITE].

Accept and process the packet without regard to the target ID

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