MPC8540 datasheet(932/1302 Pages) FREESCALE

932 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

17-8

Freescale Semiconductor

RapidIO Interface

17.2.2 Detailed Signal Descriptions

Table 17-5 describes the RapidIO interface signals in detail.

Table 17-5. RapidIO Interface Signals—Detailed Signal Descriptions

Signal

I/O

Description

RIO_RCLK

Receive clock. Free-running input clock used to capture control and data signals. RIO_RCLK is used

to capture the frame signal RIO_RFRAME and the data bus RIO_RD[0:7]. RIO_RCLK is the

differential pair of RIO_RCLK.

State

Meaning

Asserted/Negated—A clock event is determined as the rising or falling edge of RIO_RCLK.

Timing Assertion/Negation—Free-running clock. See the MPC8540 Integrated Processor

Hardware Specification for specific timing information for this signal.

RIO_RD[0:7]

Receive data. The receive data bus RIO_RD[0:7] carries packet information as well as control

symbols. Data is captured on both edges of RIO_RCLK. RIO_RD[0:7] is the differential pair of

RIO_RD[0:7]

State

Meaning

Asserted/Negated—Represents the data being received on the RapidIO interface.

Timing RIO_RD[0:7] data is captured on both the rising and falling edges of RIO_RCLK.

RIO_RFRAME

Receive frame. Non return to zero (NRZ) input. It toggles at the beginning of a packet or control

symbol. RIO_RFRAME is the differential pair of RIO_RFRAME.

State

Meaning

Asserted/Negated—Assertion is signalled by a toggling of the signal. Toggling indicates a

special packet framing event on the receive data (RIO_RD) pins.

Timing RIO_RFRAME is sampled with respect to RIO_RCLK.

RIO_TCLK

O Transmit clock out. Free-running output clock which is launched in phase with the output data,

RIO_TD, and the frame signal, RIO_TFRAME. RIO_TCLK should track the data bus RIO_TD[0:7]

through all the associated routing (board, package, and so forth). RIO_TCLK is the differential pair of

RIO_TCLK. See Section 17.1.4.1, “Transmit Clock-Select Mode,” for more information on the source

of the transmit clock.

State

Meaning

Asserted/Negated—A clock event in the transmit domain is determined as the rising or

falling edge of this signal.

Timing Assertion/Negation—RIO_TCLK is a free-running clock. Note that the RIO_TCLK is NOT

phase aligned to the device clock.

RIO_TD[0:7]

O Transmit data. Carries packet information as well as control symbols. The data bus is switched on

both edges of RIO_TCLK. RIO_TD[0:7] is the differential pair of RIO_TD[0:7].

State

Meaning

Asserted/Negated—Represents the data being transmitted on the RapidIO interface.

Timing Assertion of RIO_TD is always performed with a fixed relationship to RIO_TCLK.

MPC8540 Datasheet(PDF) 932 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 932 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL