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MPC8540 Datasheet(PDF) 933 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 933 Page - Freescale Semiconductor, Inc |
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933 / 1302 page  Memory Map/Register Definition MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 17-9 17.3 Memory Map/Register Definition The memory map for the RapidIO controller is shown in Table 17-6. RIO_TFRAME I Transmit frame. NRZ output. It toggles at the beginning of a packet or control symbol. RIO_TFRAME is the differential pair of RIO_TFRAME. State Meaning Asserted/Negated—Assertion is signalled by a toggling of the signal. Toggling indicates a special packet framing event on the transmit data (RIO_TD[0:7]) pins. Timing RIO_TFRAME is generated with respect to RIO_TCLK. RIO_TX_CLK_IN I Transmit clock in. Externally generated reference clock for the RapidIO transmit domain. RIO_TX_CLK_IN is the differential pair of RIO_TX_CLK_IN. Table 17-6. RapidIO Module Memory Map Offset Register Access Reset Section/Page RapidIO Architectural Registers 0xC_0000 DIDCAR—Device identity capability register R 0x0002_0002 17.3.1.1/17-13 0xC_0004 DICAR—Device information capability register R 0x8030_0020 17.3.1.2/17-14 0xC_0008 AIDCAR—Assembly identity capability register R/W 0x0000_0000 17.3.1.3/17-14 0xC_000C AICAR—Assembly information capability register R/W 0x0000_0100 17.3.1.4/17-15 0xC_0010 PEFCAR—Processing element features capability register R 0xE088_0009 17.3.1.5/17-15 0xC_0014 SPICAR—Switch port information capability register R 0x0000_0100 17.3.1.6/17-17 0xC_0018 SOCAR—Source operations capability register R 0x0600_FCF0 17.3.1.7/17-17 0xC_001C DOCAR—Destination operations capability register R 0x0600_FCF4 17.3.1.8/17-19 0xC_0040 MSR—Mailbox command and status register R 0x0000_0000 17.3.1.9/17-22 0xC_0044 PWDCSR—Port-write and doorbell command and status register R 0x0000_0020 17.3.1.10/17-22 0xC_004C PELLCCSR—Processing element logical layer control command and status register R 0x0000_0001 17.3.1.11/17-24 0xC_0058 Reserved R 0x0000_0000 — 0xC_005C LCSBA1CSR—Local configuration space base address 1 command and status register R/W 0x0000_0000 17.3.1.12/17-24 0xC_0060 BDIDCSR—Base device ID command and status register R/W 0x00nn_0000 17.3.1.13/17-25 0xC_0068 HBDIDLCSR—Host base device ID lock command and status register R/W 0x0000_FFFF 17.3.1.14/17-26 0xC_006C CTCSR—Component tag command and status register R/W 0x0000_0000 17.3.1.15/17-26 0xC_0100 PMBH0CSR—8/16 LP-LVDS port maintenance block header 0 command and status register R 0x0000_0002 17.3.1.16/17-27 Table 17-5. RapidIO Interface Signals—Detailed Signal Descriptions (continued) Signal I/O Description |
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