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MPC8540 Datasheet(PDF) 926 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 926 Page - Freescale Semiconductor, Inc |
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926 / 1302 page ![]() MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 17-2 Freescale Semiconductor RapidIO Interface Figure 17-1. RapidIO High Level Block Diagram The RapidIO controller also implements extra process-specific circuitry for receive clock recovery and for transmit clock and data alignment. Configuration Interface Core Request Interface RapidIO ACK Done Interface Core Response Interface Core Data Interface RapidIO Data Interface RapidIO Request Interface RapidIO Response Interface Configuration Block Outbound Queue Address/ Attributes Response Queue Data Buffer Inbound Queue Address/ Attributes Logical TxData[0:7] Ack Response Queue Address Request Layer Header Assembly Link Request Logic Packet and Control Symbol Assembly Protocol Layer CRC Generator Ack History Queue Asynchronous FIFO Ack Queue CRC Check Header Assembly MSG and Doorbell Unit Throttle Logic RxData[0:7] Asynchronous FIFO Training Idle Symbol Physical Layer Data Data Packet Control Symbols Receive Registers Ack Generator Misalign Block Transmit Registers Global Arbiter |
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