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MPC8540 Datasheet(PDF) 922 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 922 Page - Freescale Semiconductor, Inc

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
16-100
Freescale Semiconductor
PCI/PCI-X Bus Interface
The POR reset values for the affected configuration bits are described in Table 16-67.
16.5.1.1 Host Mode
When the device powers up in host mode, all inbound configuration accesses are ignored (and thus
master aborted). The ACL bit is a don’t care. The device powers up with the ability to master
transactions on the PCI bus, however in order to acknowledge memory transactions, the memory
space bit must be set.
16.5.1.2 Agent Mode
When the device powers up in agent mode, it acknowledges inbound configuration accesses.
However the device cannot master transactions or acknowledge inbound memory accesses on the
PCI bus until the appropriate configuration bits (bus master and memory space, respectively) have
been set.
16.5.1.3 Agent Configuration Lock Mode
Agent configuration lock mode is similar to agent mode with the added restriction that when the
device powers up in agent configuration lock mode, it retries all inbound configuration accesses
until the ACL bit is cleared. As in agent mode, the device in agent configuration lock mode cannot
master transactions or acknowledge inbound memory accesses on the PCI bus until the appropriate
configuration bits (bus master and memory space, respectively) have been set.
16.5.2 Nonposted Writes in PCI-X
The PCI-X block may pipeline I/O write and configuration write accesses to a target that signals
a split response. To fully serialize these non-posted writes, the processor should follow each write
transaction with a read of the same target, followed by proper barrier instructions to guarantee
completion of the read before continuing with a subsequent write. This method guarantees
completion of the write and serialization of a series of writes.
Table 16-67. Power-On Reset Values for Affected Configuration Bits
Mode
Configuration Bit
Bus Master
Memory Space
ACL
PAH
Host
1
0
X
0
Agent
0001
Agent configuration
lock
0011



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