MPC8540 datasheet(927/1302 Pages) FREESCALE

927 / 1302 page

Introduction

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

17-3

The RapidIO inbound interface receives and latches 8 double data rate (DDR) data bits. 64 bits are

accumulated in the asynchronous boundary FIFO and transferred across the asynchronous

boundary into the protocol layer. At the protocol layer, the 64 bits are split into packet header,

packet data, and control symbol information fields. After the packet header information arrives in

the inbound packet assembly logic, packets are stripped of cyclical redundancy check (CRC)

information and other transport information not required by the logical layer. The CRC is checked

at the end of a packet. Packet header information and packet data are then passed to the inbound

logical layer. The header is interpreted by the logical layer and the transaction is stored in the

inbound queue if space is available. The data is held in the inbound data queue until it is transferred

out of the RapidIO controller block and into the device. Some control symbols (acks and link

responses, for example) are passed to the outbound block for processing.

On the outbound side, requests are received from the device at the logical layer and queued in the

outbound queue. Transactions from the outbound queue are scheduled according to priority and

may be steered to the misalign block or directly to the protocol layer if global arbitration is won.

Transactions whose address and data payload are not aligned according to the RapidIO alignment

requirements are sent to the misalign block for processing. The response queue handles responses

from the device for previously received inbound requests and schedules them as transactions out

of the response queue according to priority.

Of all transactions from the outbound queue, misalign block, and the response queue, one is

prioritized subject to global arbitration to be sent to the protocol layer. At the protocol layer, the

packet CRC is performed. The protocol layer logic chooses to transmit either control symbols or

packets on the outbound RapidIO interface. The packets and control symbols are then stored in the

asynchronous boundary FIFO. The physical layer logic then reads 32-bit quantities from the FIFO

and transmits them on the outbound RapidIO interface as 8-bit symbols. While there exist no

packet or control symbols to send, the physical layer sends idle symbols. Idle symbols may also

be inserted in a packet if a throttle request is received on the inbound interface.

The following sections provide greater detail on the organization and operation of RapidIO

functionality. These sections are organized as follows:

•

Section 17.2, “External Signal Descriptions,” describes the interface signal groups, their

meanings, and timing relationships.

•

Section 17.3, “Memory Map/Register Definition,” describes the configuration, runtime,

and debug registers that constitute the programming model.

•

Section 17.4.1, “RapidIO Transaction, Packet, and Control Symbol Summary,” describes

the functional organization and operation of the design.

•

Section 17.5, “RapidIO Functionality,” provides general information about implementing

RapidIO features.

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