MPC8540 datasheet(940/1302 Pages) FREESCALE

940 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

17-16

Freescale Semiconductor

RapidIO Interface

Processor. Set for the MPC8540.

0 The RapidIO controller does not have a processor core.

1 The RapidIO controller has a processor core.

Switch. Cleared for the MPC8540.

0 The RapidIO controller is a switch.

1 The RapidIO controller is not a switch.

4–7

—

Reserved

Mailbox 0. Set for the MPC8540.

0 The RapidIO controller does not support mailbox 0.

1 The RapidIO controller supports mailbox 0.

Mailbox 1. Cleared for the MPC8540.

0 The RapidIO controller does not support mailbox 1.

1 The RapidIO controller supports mailbox 1.

Mailbox 2. Cleared for the MPC8540.

0 The RapidIO controller does not support mailbox 2.

1 The RapidIO controller supports mailbox 2.

Mailbox 3. Cleared for the MPC8540.

0 The RapidIO controller does not support mailbox 3.

1 The RapidIO controller supports mailbox 3.

Doorbell. Set for the MPC8540.

0 The RapidIO controller does not support inbound doorbells.

1 The RapidIO controller supports inbound doorbells.

13–26

—

Reserved

CTLS Common transport route. Cleared for the MPC8540.

0 The RapidIO controller does not support the large common transport route field.

1 The RapidIO controller supports the large common transport route field.

Extended features. Set for the MPC8540.

0 The extended features pointer is not valid.

1 The extended features pointer is valid.

29–31

EAS

Extended addressing support. Possesses a value of 001 for the MPC8540.

001 The RapidIO controller supports 34-bit local addresses.

010 Reserved

011 The RapidIO controller supports 50- and 34-bit local addresses.

100 Reserved

101 The RapidIO controller supports 66- and 34-bit local addresses.

110 Reserved

111 The RapidIO controller supports 60-, 50- and 34-bit local addresses.

Table 17-11. PEFCAR Field Descriptions

Bits

Name

Description

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