MPC8540 datasheet(939/1302 Pages) FREESCALE

939 / 1302 page

Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

17-15

17.3.1.4 Assembly Information Capability Register (AICAR)

The AICAR, shown in Figure 17-6, provides additional information about the assembly.

Table 17-10 describes the fields of the AICAR.

17.3.1.5 Processing Element Features Capability Register (PEFCAR)

The PEFCAR, shown in Figure 17-7, identifies major functionality provided by the RapidIO

block.

Table 17-11 describes the fields of the PEFCAR.

015 16

EFP

Reset

0000_0000_0000_0000_0000_0001_0000_0000 (Alternate value may be read from serial ROM)

Offset

0xC_000C

Figure 17-6. Assembly Information Capability Register (AICAR)

Table 17-10. AICAR Field Descriptions

Bits

Name

Description

0–15

Assembly revision. This field states the assembly revision level.

16–31

EFP

Extended features pointer. Pointer to the first entry in the extended features list.

12 13

R B M P S

0 M0 M1 M2 M3 D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTLS EF

EAS

Reset

1110_0000_1000_1000_0000_0000_0000_1001

Offset

0xC_0010

Figure 17-7. Processing Element Features Capability Register (PEFCAR)

Table 17-11. PEFCAR Field Descriptions

Bits

Name

Description

Bridge. Set for the MPC8540.

0 The RapidIO controller does not have a DRAM interface.

1 The RapidIO controller has a DRAM interface.

Memory. Set for the MPC8540.

0 The RapidIO controller does not have local address space.

1 The RapidIO controller has local address space.

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