MPC8540 datasheet(941/1302 Pages) FREESCALE

941 / 1302 page

Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

17-17

17.3.1.6 Switch Port Information Capability Register (SPICAR)

The SPICAR, shown in Figure 17-8, defines the RapidIO block’s switching capabilities.

Table 17-12 describes the fields of the SPICAR.

17.3.1.7 Source Operations Capability Register (SOCAR)

The SOCAR, shown in Figure 17-9, reflects the set of RapidIO operations that this device can

initiate. See the Parallel RapidIO Interconnect Specification for details.

015 16

23 24

R 0

00000

000000

Reset

0000_0000_0000_0000_0000_0001_0000_0000

Offset

0xC_0014

Figure 17-8. Switch Port Information Capability Register (SPICAR)

Table 17-12. SPICAR Field Descriptions

Bits

Name

Description

0–15

—

Reserved

16–23

Port total. The RapidIO controller has one RapidIO port. (SPICAR[PT] = 0x01)

24–31

Port number. This is the port number from which this register was read. This field is 0 since the MPC8540

has only one port.

45678

DCI

IOR

IKI

TIE

TIES

Reset

0000_0110_0000_0000

NWR

ATS

Reset

1111_1100_1111_0000

Offset

0xC_0018

Figure 17-9. Source Operations Capability Register (SOCAR)

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