MPC8540 datasheet(1044/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

17-120

Freescale Semiconductor

RapidIO Interface

17.8.4.4.1 Inbound Doorbell Reception

The following sequence of events occurs during reception of a doorbell message:

•

The inbox receives a doorbell message request from the RapidIO port. If the inbox is

enabled (DMR[DE] = 1) and it is not busy with another doorbell message (DSR[DB] = 1),

then the doorbell message is accepted.

•

The 16-bit information field is stored in local memory using the value of DQDPAR.

•

The enqueue pointer is incremented to point to the next doorbell queue entry in local

memory.

•

An interrupt is generated if enabled (DMR[DIQIE] = 1). The interrupt is held until the

dequeue pointer equals the enqueue pointer and the doorbell queue is empty. That is, as long

as doorbell messages exist in memory that have not been serviced and the interrupt is

enabled, the interrupt remains asserted.

17.8.4.4.2 Doorbell Queue Entry Format

This section defines the format of the doorbell information written to memory by the doorbell

controller. Each doorbell entry in the queue has two 32-bit offsets, one for target information and

one for source information. Table 17-104 shows the target information.

Table 17-105 shows the source information.

Figure 17-86 shows the doorbell queue entry fields and their related offsets.

Figure 17-86. Doorbell Entry Format

Table 17-104. Target Information Definition

Bits

Name

Description

0–23

—

Reserved

24–31

TID

Target ID field from the received doorbell packet

Table 17-105. Source Information Definition

Bits

Name

Description

0–7

—

Reserved

8–15

SID

Source ID field from the received doorbell packet

16–31

INFO

Information field from the received doorbell packet

0b000

0b100

Target info

Local Memory

Offset

Source info

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