MPC8540 datasheet(1040/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

17-116

Freescale Semiconductor

RapidIO Interface

queue, the message unit controller starts a new message operation with the control parameters

specified by the descriptor. Table 17-103 describes the outbound message unit descriptor.

Figure 17-83 shows the queue dequeue pointer and an associated descriptor. The descriptor is only

valid if the enqueue and dequeue pointers are not equal.

Figure 17-83. Descriptor Dequeue Pointer and Descriptor

17.8.4.2.5 Outbox Controller Interrupts

The outbox generates the following four interrupts, which can be individually enabled.

•

Queue overflow interrupt. Generated if the enqueue pointer passes the dequeue pointer and

the queue is full and the interrupt is enabled. OSR[QOI] is set if OMR[QOIE] is set.

•

Queue full interrupt. Generated if the enqueue pointer catches up to the dequeue pointer,

the queue is not empty, and the interrupt is enabled. OSR[QFI] is set if OMR[QFIE] is set.

Table 17-103. Outbound Message Unit Descriptor Summary

Offset

Descriptor Field

Description

0x00

Reserved

—

0x04

Source address

Source address of the message operation. After the message controller reads the

descriptor from memory, this field is loaded into the source address register.

0x08

Destination port

Destination port of the message operation. After the message controller reads the

descriptor from memory, this field is loaded into the destination port register.

0x0C

Destination attributes Transaction attributes of the message operation. After the message controller reads the

descriptor from memory, this field is loaded into the destination attributes register.

0x10

Reserved

—

0x14

Reserved

—

0x18

Double-word count

Number of double words for the message operation. After the message controller reads

the descriptor from memory, this field is loaded into the double-word count register.

0x1C

Reserved

—

Descriptor Dequeue Pointer Address Register

Descriptor

0x00

0x08

0x18

0x10

0x04

Destination Port

Reserved

Double-Word Count

Reserved

Local Memory

Offset

0x14

Source Address

0x0C

Reserved

0x1C

Destination Attributes

Reserved

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