MPC8540 datasheet(1037/1302 Pages) FREESCALE

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RapidIO Message Unit

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

17-113

OMR[MUI] = 1 and repeat this process until the descriptor queue is full. Hardware performs the

enqueue pointer address calculation, queue fullness and queue wrap checks and software writes

new descriptors using the computed enqueue pointer address.

In list mode, software can build one or more descriptors in memory before initializing the outbox

controller registers. Software is responsible for maintaining and controlling ODQEPAR. Software

is also responsible for keeping track of queue fullness and wrap conditions. OMR[MUI] is not

used in this mode.

The outbox message controller takes descriptors off the tail of the queue and processes them,

incrementing ODQDPAR to point to the next descriptor in the queue and repeats this process until

the enqueue and dequeue pointers are equal.

Figure 17-82 shows a sample structure of the outbox portion of the outbox message controller, a

descriptor list queue, and the message data queue. In this example, the descriptor list queue has

eight entries, four of which are currently valid. The processor core adds descriptors to the head of

the queue and the outbox message controller takes them off from the tail.

Figure 17-82. Outbound Message Queue Structure

The sequence of events to start and complete a transfer by adding descriptors after initializing the

message unit in normal chaining mode is as follows:

•

Initialize ODQDPAR and ODQEPAR to the same value for proper operation.

•

Initialize the outbound mode register message unit transfer mode bit, OMR[MUTM] = 0,

to indicate chaining mode and set OMR[MUS] = 0 to disable the data message controller.

Other control parameters must also be initialized in the mode register.

•

Set OMR[MUS], which enables the outbox controller and causes ODQDPAR to be saved

as the base address of the circular queue. The enqueue pointer is incremented when

OMR[MUI] is set by software. If the enqueue and dequeue pointers are not equal, the

descriptor fetch begins immediately from the address pointed to by ODQDPAR. If they are

Outbound

Message

Data

Message

Data

Message

Data

Desc

Enqueue pointer

Dequeue pointer

Outbound

Message

Controller

Local Memory

Packets to

Message

Data

Processor Core

Enqueue and Tail Pointers

RapidIO

Interface

Descriptor List

Queue

Message Data Queue

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