MPC8540 datasheet(1041/1302 Pages) FREESCALE

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RapidIO Message Unit

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

17-117

•

Queue empty interrupt. Generated if the dequeue pointer catches up to the enqueue pointer

and the interrupt is enabled. OSR[QEI] is set if OMR[QEIE] is set.

•

End-of-message interrupt. Generated after the completion of each message if enabled.

OSR[EOMI] is set if ODATR[EOMIE] is set.

17.8.4.2.6 Special Error Case Condition

If a data message is in progress and the outbox encounters an error with one of the segments, it

causes an error at the recipient by placing an illegal field in the packet to cause the error. This

prevents the recipient from using data in the message. For example, if the outbox controller reads

message data from its DRAM memory and gets an uncorrectable ECC error. This scheme prevents

the recipient from hanging or using bad data.

17.8.4.3 Inbox Controller Operation

The inbox controller is responsible for receiving messages and placing them in a circular queue in

local memory. Although, it only supports one mailbox and one letter, the inbox controller can

receive messages with any mailbox or letter number. Furthermore, the inbox can receive segments

of a message in any order. The address of where to write the message is computed as: Base address

+ (msgseg * ssize in double words). Unlike the outbox where the enqueue pointer is controlled by

software and the dequeue pointer is controlled by hardware, the inbox controls the enqueue pointer

and software controls the dequeue pointer.

Figure 17-84 shows a sample structure of the inbound mailbox message frames and the frame

pointers. In this example, the frame queue has eight entries, three of which are currently valid. The

mailbox controller adds frames to the head of the queue and the processor core takes them off from

the tail. After processing a message, the processor core writes the inbox mode register mailbox

increment bit (IMR[MI]) to point to the next message frame in the queue. This process is repeated

for each received message.

Figure 17-84. Inbound Mailbox Structure

Message

Frame

Message

Frame

Message

Frame

Enqueue pointer

Dequeue pointer

Processor Core Read

Inbound

Mailbox

Port

Local Memory

Packets from

RapidIO Interface

Frame Queue

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