MPC8540 datasheet(1045/1302 Pages) FREESCALE

1045 / 1302 page

RapidIO Message Unit

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

17-121

17.8.4.4.3 Retry Response Conditions

There is one condition in which a doorbell message is logical layer retried (response retry):

•

Doorbell request received and the doorbell circular queue is full

17.8.4.4.4 Error Response Conditions

Several conditions cause a logical layer error response (response error):

•

Doorbell controller is error state

•

Doorbell controller is not enabled

17.8.4.4.5 Doorbell Controller Interrupts

The doorbell controller generates the following two different interrupts that can be individually

enabled:

•

Doorbell-in-queue interrupt. Generated each time the circular queue becomes not empty

and the interrupt is enabled. DSR[DIQI] is set if DMR[DIQIE] is set

•

Queue full interrupt. Generated each time the circular queue becomes full and the interrupt

is enabled. DSR[QFI] is set if DMR[QFIE] is set

17.8.4.5 Port-Write Controller Structure

The implementation of the port-write controller is very similar to the inbound message hardware.

The port-write is intended as an error reporting mechanism from an end-point-free device to a

control processor or other system host.

Figure 17-87 shows an example of the structure of the inbound queue and pointer. The port-write

queue only contains one entry with a fixed size of 64 bytes and aligned to a cache line boundary.

The port-write controller puts an incoming port-write data payload in the location indicated by the

pointer and then sets its PWSR[QFI] if PWMR[QFIE] is set. The processor core must explicitly

clear PWSR[QFI] after servicing the port-write. While the full bit is set, or if it is busy handling a

previous port-write, or the port-write controller is not enabled, the controller silently discards all

incoming port-write packets.

MPC8540 Datasheet(PDF) 1045 Page - Freescale Semiconductor, Inc