MPC8540 datasheet(1046/1302 Pages) FREESCALE

1046 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

17-122

Freescale Semiconductor

RapidIO Interface

Figure 17-87. Inbound Port-Write Structure

Upon successfully receiving a port-write transaction, if PWMR[QFIE] is set, PWSR[QFI] is set

and an interrupt is generated to the processor core.

17.9 Initialization and Application Information

The following steps outline the RapidIO port initialization procedure:

1. Configure the transmit clock select pins to select either the receive clock, externally

provided transmit clock or the platform clock for the RapidIO transmit clock domain.

2. Initialize the host/agent field (using configuration pins) to put the end-point in host or

agent mode over RapidIO.

3. Initialize the Device ID field (using configuration pins) to assign a device identifier at

power-on reset.

4. The address translation and mapping unit (ATMU) for RapidIO must be initialized for

RapidIO accesses.

5. Clear the CR[AA] bit to allow the logic to detect an error when it receives packets with a

target ID not equal to its own.

6. Follow the system initialization and discovery mechanism described in the

inter-operability portion of the Parallel RapidIO Interconnect Specification for

configuring the RapidIO system.

Port-write

64-byte Entry

Pointer

Processor Core Read

Inbound

Port-write

Port

Local Memory

Port-write packets from

RapidIO interface

Port-write Queue

MPC8540 Datasheet(PDF) 1046 Page - Freescale Semiconductor, Inc