MPC8540 datasheet(1042/1302 Pages) FREESCALE

1042 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

17-118

Freescale Semiconductor

RapidIO Interface

The sequence of events that takes place during the reception of a data message is as follows:

•

The inbox receives a message request from the RapidIO port. If the inbox is enabled

(IMR[ME] = 1) and it is not busy with another message (ISR[MB] = 1), then the message

is accepted.

•

The address is computed for each segment of the message (up to 16 segments/packets per

message) using the value of the inbound frame queue enqueue pointer address registers and

properly adjusted based on segment number.

•

Data is stored in the circular queue in local memory at the computed address.

•

After the entire message is received, the enqueue pointer is incremented to point to the next

message frame in local memory.

•

An interrupt is generated if enabled (IMR[MIQIE] = 1). The interrupt is held until the

dequeue pointer equals the enqueue pointer and the message queue is empty. That is, as

long as messages exist in memory that have not been serviced and the interrupt is enabled,

the interrupt remains asserted.

17.8.4.3.1 Retry Response Conditions

The following two conditions generate a logical layer retry (response retry):

•

Inbox receives a message but is busy handling another message

•

Local memory circular queue is full and a message is received

17.8.4.3.2 Error Response Conditions

Several conditions generate a logical layer error response (response error) as follows:

•

Inbox receives a message and it is not enabled

•

Inbox is in an error state caused by a previous message

•

Inbox receives a segment that exceeds the message length (msgseg > msglen)

•

Inbox receives a message segment being processed with a bad message length

•

Inbox receives a duplicate segment of a message being processed that was already received

successfully

17.8.4.3.3 Inbox Controller Interrupts

The inbox generates the following interrupts, which can be individually enabled:

•

Message-in-queue interrupt. This interrupt is generated each time the circular queue

becomes not empty and the interrupt is enabled. ISR[MIQI] is set if IMR[MIQIE] is set.

•

Queue full interrupt. This interrupt is generated each time the circular queue becomes full

and the interrupt is enabled. ISR[QFI] is set if IMR[QFIE] is set.

MPC8540 Datasheet(PDF) 1042 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 1042 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL