MPC8540 datasheet(1039/1302 Pages) FREESCALE

1039 / 1302 page

RapidIO Message Unit

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

17-115

Software must guarantee that descriptors are not added to an already full queue. This can be

accomplished in one of two ways:

•

When OMR[QFIE] is set, hardware tracks queue fullness in normal chaining mode and

reports an interrupt if the queue becomes full. After the interrupt bit is set, it is the

responsibility of the software to clear the interrupt condition by setting OSR[QFI]. QFI is

not cleared with the write if the queue is still full. When QFI is cleared, the queue is no

longer full and a descriptor may be added to the queue.

•

When OMR[QFIE] is cleared or if operating in list chaining mode, OSR[QFI] is not set by

hardware on a queue full condition, and it is the responsibility of the software to calculate

queue fullness before adding a new descriptor. Software can detect queue fullness by

comparing the enqueue (ODQEPAR) and the dequeue pointer (ODQDPAR) and

monitoring the queue busy bit (OSR[MUB]). The queue is full if the enqueue and dequeue

pointers are equal and the queue busy bit is set.

The following process adds a descriptor to the circular memory queue in normal mode:

•

Ensure that the circular queue is not full by using either of the above methods.

•

Write the descriptor to be enqueued to the 32 bytes pointed to by the enqueue pointer

(ODQEPAR).

•

Write OMR[MUI] = 1 keeping the same values of all the other bits in the OMR.

•

A new descriptor may be added by incrementing the enqueue pointer if the queue is not full.

17.8.4.2.3 Switching Between Direct and Chaining Modes

The message unit architecture allows switching from direct mode to chaining mode and vice-versa

after all the required parameters have been initialized in the appropriate registers and when the

message unit is not busy with a current transfer as indicated by OSR[MUB] being cleared. When

switching from direct mode to chaining mode, if OMR[MUS] is cleared and then set, the message

unit is re-initialized to chaining mode and the outbound descriptor queue dequeue pointer address

is saved as the new base address of the circular queue in memory. If this is not desired,

OMR[MUS] should stay set when switching from direct mode to chaining mode. When the

enqueue and dequeue pointers are not equal, the message unit begins the new descriptor fetch

while retaining the same circular queue parameters as the previous chaining mode transfer. When

switching from chaining mode to direct mode, OMR[MUS] must be cleared and then set. This has

no effect on the circular queue parameters thereby saving the queue state for the next chaining

mode transfer.

17.8.4.2.4 Descriptor Format

Message descriptors contain information for the message unit controller to transfer data. Software

must ensure that each descriptor is aligned on a 32-byte boundary. For each descriptor in the

MPC8540 Datasheet(PDF) 1039 Page - Freescale Semiconductor, Inc

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