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MSP430 Datasheet(PDF) 36 Page - Texas Instruments

Part # MSP430
Description  AFEx8101 16-Bit and 14-Bit, Low-Power DACs With Voltage Reference and Diagnostic ADC for 4-mA to 20-mA Loop-Powered Applications
PDF  88 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

MSP430 Datasheet(HTML) 36 Page - Texas Instruments

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7.3.2.8 ADC Bypass
To test the offset, modify the ADC data path by programming the bypass data register, ADC_BYP.DATA (2Eh).
This read/write register is used in two different ways.
First, this bypass data register is used as a substitute for the ADC_OFFSET by setting the
ADC_BYP.OFST_BYP_EN to 1.
Second, the ADC_BYP.DATA is used as the readback register for the data for the different settings of the custom
channel sequencer. The data are replaced by setting the ADC_BYP.DATA_BYP_EN bit. When this bit is set to 1,
the ADC conversion is bypassed, and the value of ADC_BYP.DATA is used in the readback channel. This setting
is used to test the alarm settings of the ADC.
When the ADC bypass is unused, set the ADC_BYP.DATA to 000h.
Figure 7-11 shows the ADC bypass data flow.
ADC_BYP.DATA
Register 2Eh
0
1
0
1
ADC_OFFSET
Register 28h
ADC_AIN0
Register 24h
ADC_AIN1
Register 25h
ADC_TEMP
Register 26h
ADC_SD_MUX
Register 27h
+
+
ADC_BYP.
OFST_BYP_EN
Register 2Eh
ADC_BYP.
DATA_BYP_EN
Register 2Eh
ADC Data
From ADC MUX
ADC.
ADC_OUT
Register 2Dh
ADC
MUX
07FFh – OFFSET
Stored as 2’s Complement
CCS Pointer
Read and Writeable
for Testing
Figure 7-11. ADC Bypass Data Flow
7.3.3 Programmable Out-of-Range Alarms
The AFEx8101 are capable of continuously analyzing the supplies, external ADC inputs, DAC output voltage,
reference, internal temperature, and other internal signals for normal operation.
Normal operation for the conversion results is established through the lower- and upper-threshold registers.
When any of the monitored inputs are out of the specified range, the corresponding alarm bit in the alarm status
registers is set.
The alarm bits in the alarm status registers are latched. The alarm bits are referred to as being latched because
the alarm bits remain set until read by software. This design makes sure that out-of-limit events cannot be
missed if the software is polling the device periodically. All bits are cleared when reading the alarm status
registers, and all bits are reasserted if the out-of limit condition still exists on the next monitoring cycle.
All of the alarms can be set to activate the ALARM pin. The ALARM pin works as an interrupt to the host so that
the host can query the alarm status registers to determine the alarm source. Any alarm event activates the pin
as long as the alarm is not masked in the ALARM_STATUS_MASK register. When an alarm event is masked,
the occurrence of the event sets the corresponding status bit in the alarm status registers, but does not activate
the ALARM pin.
In addition, Section 7.3.3.1 describes how the alarm action can be individually configured for each alarm. When
the alarm event is cleared, the DAC is reloaded with the contents of the DAC active registers, which allows the
DAC outputs to return to the previous operating point without any additional commands.
AFE78101, AFE88101
SLASF21 – DECEMBER 2022
www.ti.com
36
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: AFE78101 AFE88101



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