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7.6.1.9 ADC_CFG Register (Offset = 8h) [Reset = 8810h]

Return to the Register Map.

Table 7-20. ADC_CFG Register Field Descriptions

Bit

Field

Type

Reset

Description

BUF_PD

R/W

ADC Buffer Power-down

0h = ADC buffer enabled; 1h = ADC buffer powered down (default)

14-8

HYST

R/W

Hysteresis

The number of codes of hysteresis used when a threshold is exceeded for an ADC

measurement of AIN0/AIN1/TEMP.

7-5

FLT_CNT

R/W

Fault Count

Number of successive faults to trip an alarm.

Number of successive faults is programmed value + 1 (1-8 faults).

AIN_RANGE

R/W

ADC Analog Input Range

Can only be set if PVDD ≥ 2.7 V to use 2.5-V range for AIN0 and AIN1 inputs.

0h = 2 × VREF; 1h = 1 × VREF (default)

EOC_PER_CH

R/W

ADC End-of-Conversion for Every Channel

Sends an EOC pulse at the end of each channel instead of at the end of all the channels.

0h = EOC after last channel (default); 1h = EOC for every channel

2-1

CONV_RATE

R/W

ADC Conversion Rate

This setting only affects the conversion rate for channels AIN0 and AIN1. Rates are based

on a 76.8-kHz ADC clock. All other channels use 2560 Hz.

0h = 3840 Hz (default)

1h = 2560 Hz

2h = 1280 Hz

3h = 640 Hz

DIRECT_MODE R/W

Direct Mode Enable

0h = Auto mode (default); 1h = Direct mode

7.6.1.10 ADC_INDEX_CFG Register (Offset = 9h) [Reset = 0080h]

The ADC custom channel sequencing configuration is shown in Table 7-21.

Return to the Register Map.

Table 7-21. ADC_INDEX_CFG Register Field Descriptions

Bit

Field

Type

Reset

Description

15-8

RESERVED

7-4

STOP

R/W

Custom Channel Sequencer Stop Index

CCS index to stop ADC sequence. Must be ≥ START. If not, STOP is forced to = START.

0h = OFFSET

1h = AIN0

2h = AIN1

3h = TEMP

4h = SD0 (VREF)

5h = SD1 (PVDD)

6h = SD2 (VDD)

7h = SD3 (ZTAT)

8h = SD4 (VOUT) (default)

9h through Fh = GND

3-0

START

R/W

Custom Channel Sequencer Start Index

CCS index to start ADC sequence.

0h through Fh = Same as STOP field (0h is default)

AFE78101, AFE88101

SLASF21 – DECEMBER 2022

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