MSP430 datasheet(47/88 Pages) TI

47 / 88 page

SDO

SDI

R/W (1b)

Don’t Care

Valid Data

Hi-Z

Output Frame (n-1)

Status (7b)

Data Word (16b)

Address (7b)

Data Word (16b)

R/W (1b)

Next Frame (n+1), Command or NOP

Output Frame (n)

Input Frame (n)

SCLK

22~16

15~0

Figure 7-20. SPI Frame Details (CRC Disabled)

For a valid frame, a full frame length of data (24 bits if CRC is disabled or 32 bits if CRC is enabled) must be

transmitted before CS is brought high. If CS is brought high before the last falling SCLK edge of a full frame,

then the data word is not transferred into the internal registers. If more than a full frame length of falling SCLK

edges are applied before CS is brought high, then the last full frame length number of bits are used. In other

words, if the number of falling SCLK edges while CS = 0 is 34, then the last 32 SCLK cycles (or 24 if CRC is

disabled) are treated as the valid frame. The device internal registers are updated from the SPI shift register on

the rising edge of CS. To start another serial transfer, bring CS low again. When CS is high, the SCLK and SDI

signals are blocked and the SDO pin is high impedance.

7.5.2.2 SPI Read and Write

The SDI input bit is latched on the SCLK falling edge. The SDI pin receives right-justified data. At the rising edge

of CS, the right-most (last) bits are evaluated as a frame. Extra clock cycles (exceeding frame length) during the

frame begin to output on SDO the SDI data delayed by one frame length.

A read operation is started when R/W bit is 1. The data word input for SDI is ignored in the read command

frame. Send the subsequent read or write command frame into SDI to clock out the data of the addressed

requested data. The read register value is output most significant bit first on SDO on successive edges (rising or

falling based on CONFIG.FSDO setting) of SCLK.

A write operation starts when R/W bit is 0. The SDO output to a write command, delivered in the next frame,

contains status bits, data described in Table 7-8, and if the CRC is enabled, an 8-bit CRC for the output frame.

Table 7-8. Command Functions

COMMAND BIT

SDI INPUT DATA WORD

SDO RESPONSE DATA WORD(1)

Write (R/W = 0)

Data to be written (16b)

0x0000

Read (R/W = 1)

Ignored(2)

(1)

Response data portion in next frame output.

(2)

The input bits are included in the calculation for CRC, if enabled (see Section 7.5.2.3).

Valid SDO output is driven only when CS = 0 and CONFIG.DSDO = 0; otherwise, the SDO pin remains Hi-Z to

save power. The SDO data bits are left-justified within the frame, meaning the most significant bit is produced on

the line (subject to timing details) when CS is asserted low (bit is driven by falling edge of CS). The subsequent

bits in the frame are driven by the rising SCLK edge when CONFIG.FSDO = 0 (default). To drive the SDO data

on the falling edge of SCLK, set CONFIG.FSDO = 1. This setting effectively gives the SDO data an additional ½

clock period for setup time, but at the expense of hold time.

The frame output on SDO contains the command bit of the input that generated the frame (previous input frame),

followed by seven status bits (see Figure 7-19). When an input frame CRC error is detected, the status bit

CRC_ERR = 1. If there is no input frame CRC error, then CRC_ERR = 0. See Table 7-9 for details.

7.5.2.3 Frame Error Checking

If the AFEx8101 are used in a noisy environment, use the CRC to check the integrity of the SPI data

communication between the device and the system controller. This feature is enabled by default and is controlled

www.ti.com

AFE78101, AFE88101

SLASF21 – DECEMBER 2022

Submit Document Feedback

Product Folder Links: AFE78101 AFE88101

MSP430 Datasheet(PDF) 47 Page - Texas Instruments

MSP430 Datasheet(HTML) 47 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

Datasheet Download

Link URL