MSP430 datasheet(43/88 Pages) TI

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7.4 Device Functional Modes

7.4.1 DAC Power-Down Mode

Power-down mode facilitates rapid turn-off of the voltage at the DAC output. The DAC can be set to enter and

exit power-down mode through hardware, software, or automatically in response to an alarm event. The DAC

output is specified for glitch-free performance when going into and out of power-down mode.

Power-down mode is also be enabled by setting DAC_CFG.PD to 1. In power-down mode, the DAC output

amplifier powers down and the DAC output pin is put into the Hi-Z configuration. The DAC output remains in

power-down mode until the DAC output is re-enabled.

Alarm control of the power-down mode is enabled by setting the alarm events as DAC power-down sources. The

alarm events that trigger the DAC output power-down state must be specified in the ALARM_ACT register. After

the alarm bit is cleared, the DAC returns to normal operation, as long as no other power-down controlling alarm

event has been triggered.

The DAC register does not change when the DAC enters power-down mode, which enables the device to return

to the original operating point after return from the power-down mode. Additionally, the DAC register can be

updated while the DAC is in power-down mode, thus allowing the DAC to output a new value upon return to

normal operation.

7.4.2 Reset

There are three reset mechanisms in the device: a power-on reset (POR), a RESET pin, and the SW_RST

command that can be sent through the either the SPI or by UBM.

When power is first applied to the device, a POR circuit holds the device in reset until all supplies reach

the specified operating voltages. The power-on reset returns the device to a known operating state in case

a brownout event occurs (when the supplies have dipped below the minimum operating voltages). The POR

starts all digital circuits in reset as the supply settles, and releases them to make sure that the device starts in

the default condition and loads the OTP memory. After the OTP memory has been loaded, the ALARM pin is

released. At this time, communication with the device is safe. This tPOR time is less than 100 µs.

The devices also have a RESET pin that is used as a hardware reset to the device. Send the RESET pin low for

a minimum of 100 ns (tRESET) to reset the device. A delay time of 10 μs (tRESETWAIT) is required before sending

the first serial interface command as the device latches and releases the reset. The release of the internal

reset state is synchronized to the internal clock. The RESET pin resets the SPI and the UART interfaces, the

watchdog timer, the internal oscillator, and the device registers. RESET does not reload the OTP memory.

The command to RESET.SW_RST = 0xAD resets the device as a software reset. The command is decoded at

the rising edge of CS with an SPI command or during the stop bit of the last character of a UBM frame. Set

UBM.REG_MODE again to put the device back into UBM when resetting the device in UBM. After sending the

RESET command, no delay time is required before sending the first serial interface command as the device

latches and releases the reset. The reset is synchronized to the falling edge of the internal clock and is released

well before the next rising edge. The ALARM pin pulses low for the width of the internal reset. This pulse

duration is less than 20 ns. This command resets the SPI and the UART interface, and the watchdog timer, but

does not reset the internal oscillator. The software reset also reloads internal factory trim registers if properly

configured in the SPECIAL_CFG register. The SPECIAL_CFG register is only reset with a POR.

The POR and hardware reset place the internal oscillator into a reset condition, which holds the clock low.

When these two signals are released, there is a delay of a few microseconds before the first rising edge of

the clock. The hardware reset, RESET, pulse width must be at least 100 ns to allow the oscillator to properly

reset. The SW_RST command is a short pulse. This pulse is not long enough to adequately reset the oscillator.

The SW_RST is asserted with a falling edge of the clock. As a result of the long oscillator period, the design

architecture provides that all devices are out of reset by the next rising edge.

Figure 7-16 shows the reset tree.

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AFE78101, AFE88101

SLASF21 – DECEMBER 2022

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