MSP430 datasheet(46/88 Pages) TI

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CONFIG.IRQ_PIN_EN = 1 is set, then the SDO pin functions as the IRQ output. If CONFIG.CLR_PIN_EN =

1 is set, then the SDI pin controls the clear pin function.

IOVDD

UART

(UBM)

Control Logic

SDI

SDO

SCLK

UARTOUT

UARTIN

System

Controller

AFE

Minimum

Functionality

RESET

SCLR

GND

IOVDD

UART

(UBM)

Control Logic

SDI

SDO

SCLK

UARTOUT

UARTIN

Interrupt

Clear

Reset

System

Controller

AFE

Maximum

Functionality

RESET

SCLR

GND

IOVDD

CLK_OUT

Monitor

Figure 7-18. UBM (UART Interface) Connections

7.5.2 Serial Peripheral Interface (SPI)

The AFEx8101 are controlled over a versatile four-wire serial interface (SDIN, SDO, SCLK, and CS). The

interface operates at clock rates of up to 12.5 MHz and is compatible with SPI, QSPI, Microwire, and digital

signal processing (DSP) standards. The SPI communication command consists of a read or write address, a

data word, and an optional CRC byte.

The SPI can access all register addresses except for the UBM register. Read-only and read-write capability is

defined by register (see Table 7-10). The SPI supports both SPI Mode 1 (CPOL = 0, CPHA = 1) and SPI Mode 2

(CPOL = 1, CPHA = 0). The default SCLK value is low for SPI Mode 1 and high for SPI Mode 2. See Section 6.7

for timing diagrams in each mode. The serial clock, SCLK, can be continuous or gated.

7.5.2.1 SPI Frame Definition

Subject to the timing requirements listed in the Timing Requirements, the first SCLK falling edge immediately

following the falling edge of CS captures the first frame bit. Subject to the same requirements, the last SCLK

falling edge before the rising edge of CS captures the last bit of the frame. Figure 7-19 shows that the SPI

shift register frame is 32-bits wide, and consists of an R/W bit, followed by a 7-bit address, and a 16-bit data

word. The 8-bit CRC is optional (enabled by default) and is disabled by setting CONFIG.CRC_EN = 0 (see also

Section 7.5.2.3). Figure 7-20 shows that when the CRC is disabled, the frame is 24-bits wide.

SDO

SDI

Don’t Care

Valid Data

Hi-Z

Output Frame (n-1)

Status

Details

CRC_ERR

Next Frame (n+1), Command or NOP

1'b0

RESET

1'b0

GEN_IRQ

ALARM_IRQ

Address (7b)

Data Word (16b)

CRC (8b)

R/W (1b)

Status (7b)

Data Word (16b) CRC (8b)

Output Frame (n)

Input Frame (n)

SCLK

30~24

23~8

7~0

Figure 7-19. SPI Frame Details (Default, CRC Enabled)

AFE78101, AFE88101

SLASF21 – DECEMBER 2022

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