MSP430 datasheet(48/88 Pages) TI

48 / 88 page

by the CONFIG.CRC_EN bit. If the CRC is not required in the system, disable frame error checking through the

CRC_EN bit, and switch from the default 32-bit frame to the 24-bit frame.

Frame error checking is based on the CRC-8-ATM (HEC) polynomial: x8 + x2 + x + 1 (9'b100000111).

For the output register readback, the AFEx8101 supply the calculated 8-bit CRC for the 24 bits of data provided,

as part of the 32-bit frame.

The AFEx8101 decodes 24-bits of the input frame data and the 8-bit CRC to compute the CRC remainder. If no

error exists in the frame, the CRC remainder is zero. When the remainder is nonzero (that is, the input frame has

single-bit or multiple-bit errors) the ALARM_STATUS.CRC_ERR_CNT bits are incremented. A bad CRC value

prevents execution of commands to the device.

When the CRC error counter reaches the limit programmed in CONFIG.CRC_ERR_CNT, the CRC_FLT status

bit is set in the ALARM_STATUS register. The fault is reported (as long as the corresponding mask is not set)

as an ALARM_IRQ on SDO during the next frame. The ALARM pin asserts low if enabled by the alarm action

configuration (see Section 7.3.3.1).

The CRC_ERR status bit (see Figure 7-19) in the SDO frame is not sticky and is only reported for the

previous frame. The ALARM_STATUS.CRC_FLT bit is sticky and is only cleared after a successful read of

the ALARM_STATUS register. Read the GEN_STATUS or ALARM_STATUS registers to clear any sticky bits that

are set.

The sticky status bits are cleared at the start of the readback frame and are latched again at the end of the

readback frame. Therefore, if the fault condition previously reported in the status register is no longer present

at the end of the readback frame, and the data are received by the microcontroller with the CRC error, the fault

information is lost. If a robust monitoring of the status bits is required in a noisy environment, use the IRQ pin

in combination with the status mask bits to find out the status of each fault before clearing the status bits. Set

the CONFIG.IRQ_LVL bit to monitor the signal level on the IRQ pin, and unmask each status bit one at a time to

retrieve the information from the status registers.

7.5.2.4 Synchronization

The AFEx8101 register map runs on the internal clock domain. Both the SPI and UBM packets are synchronized

to this domain. This synchronization adds a latency of 0.4 µs to 1.22 µs (1.5 internal clocks), with respect to the

rising edge of CS or the STOP bit of the last byte of the UBM packet.

The effect of clock synchronization on UBM communication is not evident because of the lower speed and

asynchronous nature of UBM communication.

In SPI mode, if changing register bits CONFIG.DSDO, CONFIG.FSDO, or CONFIG.CRC_EN, keep CS high for

at least two clock cycles before issuing the next frame. Frame data corruption can occur if the two extra cycles

are not used. The following are examples of frame corruption:

• Setting CONFIG.DSDO = 0: SDO begins to drive in the middle of the next frame.

• Changing CONFIG.FSDO: The launching edge of SDO changes in the middle of the next frame.

• Setting CONFIG.CRC_EN = 1: The next frame has a CRC error because the CRC is enabled in the middle of

the frame.

Send a NOP command (SDI = 0x00_0000) after setting the DSDO, FSDO, and CRC_EN bits to prevent the

corrupted frames from impacting communication. Sending a NOP after CONFIG.CRC_EN is set still generates

a CRC error, and is reported in the STATUS portion of SDO. To avoid false errors, wait approximately 2 µs after

setting CONFIG.CRC_EN before sending the next frame.

AFE78101, AFE88101

SLASF21 – DECEMBER 2022

www.ti.com

Submit Document Feedback

Product Folder Links: AFE78101 AFE88101

MSP430 Datasheet(PDF) 48 Page - Texas Instruments

MSP430 Datasheet(HTML) 48 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

Datasheet Download

Link URL