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MSP430 Datasheet(PDF) 66 Page - Texas Instruments |
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MSP430 Datasheet(HTML) 66 Page - Texas Instruments |
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66 / 88 page  7.6.1.22 GEN_STATUS Register (Offset = 21h) [Reset = 1180h] Return to the Register Map. Table 7-33. GEN_STATUS Register Field Descriptions Bit Field Type Reset Description 15 ALARM_IRQ R 0h Alarm IRQ OR of all the unmasked bits in the ALARM_STATUS register. 0h = All of the unmasked bits of the ALARM_STATUS register are low 1h = At least one of the unmasked bits in the ALARM_STATUS register is high 14-13 RESERVED R 0h 12 OTP_BUSY R 1h OTP Busy Status = 1h at power up while the OTP is being loaded into the trim latches. 0h = OTP has completed loading into the device 1h = OTP is being loaded into the device 11 RESERVED R 0h 11-9 RESERVED R 0h 8 RESET R 1h Device Reset Occurred. Status only. Does not feed IRQ. Sticky, cleared by reading register, unless condition still persist. 0h = Device has not reset since last read of register 1h = Device has reset since last read of register 7 SR_BUSYn R 1h Slew Rate Not Busy. Maskable fault. 0h = DAC is slewing to the target code 1h = DAC_OUT has reached the DAC_DATA. If slew rate is disabled, then this signal produces a rising edge within 3 internal clock cycles. If slew rate is enabled, this signal creates an IRQ event when the DAC_OUT has reached the DAC_DATA. At this time, slew rate can be safely disabled. If slew rate is disabled prior to DAC_OUT = DAC_DATA then a jump of DAC_OUT occurs. This can cause an unwanted fast transition on VOUT. 6 ADC_EOC R 0h ADC End of Conversion (EOC). Maskable fault. Sticky, cleared by reading register, unless condition still persist. 0h = No EOC since last read of register; 1h = ADC end of conversion 5 ADC_BUSY R 0h ADC Busy. Status only. Does not feed IRQ. Active signal, set as long as condition is true. 0h = No ADC activity; 1h = ADC is actively converting 4 PVDD_HI R 0h PVDD High. Status only. Does not feed IRQ. Set as long as condition is true. 0h = PVDD < 2.7 V; 1h = PVDD ≥ 2.7V 3 BREAK_ FRAME_ERR R 0h Incorrect Stop Bit During Break Character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No break frame error; 1h = Break frame error 2 BREAK_ PARITY_ERR R 0h Incorrect parity (ODD) bit during break character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No break parity error; 1h = Break parity error 1 UART_ FRAME_ERR R 0h Incorrect stop bit during UART character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No UART frame error; 1h = UART frame error 0 UART_ PARITY_ERR R 0h Incorrect parity (ODD) bit during UART character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No UART parity error; 1h = UART parity error AFE78101, AFE88101 SLASF21 – DECEMBER 2022 www.ti.com 66 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AFE78101 AFE88101 |
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