ADM7151 datasheet(38/45 Pages) AD

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Data Sheet

LT3097

APPLICATIONS INFORMATION

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Rev. 0 | 38 of 45

Unlike most linear regulators, the LT3097 does not use a voltage

reference. Instead, the LT3097 uses a 100 μA current reference

each for the positive regulator and the negative regulator. The

current reference of the positive regulator operates with a typical

noise-current level of 20 pA/√Hz (6 nA rms over a 10 Hz to 100

kHz bandwidth). The resultant positive voltage noise equals the

current noise multiplied by the SETP resistor value, which, in turn,

is RMS summed with the noise of the error amplifier of the positive

regulator and the thermal noise of the SETP resistor, √4kTRSETP,

where k = Boltzmann’s constant (1.380649 × 10–23J/K), and T is

the absolute temperature. The current reference of the negative

regulator operates with a typical noise-current level of 27 pA/√Hz

(8 nA rms over a 10 Hz to 100 kHz bandwidth). The resultant

negative voltage noise equals the current noise multiplied by the

SETN resistor value, which, in turn, is RMS summed with the noise

of the error amplifier of the negative regulator and the thermal noise

of the SETN resistor, √4kTRSETN, where k = Boltzmann’s constant

(1.380649 × 10–23J/K), and T is the absolute temperature.

One problem that conventional linear regulators face is that the

resistor-divider setting the output voltage gains up the reference

noise. In contrast, the unity-gain follower architecture of the LT3097

presents no gain from the SETP/SETN pin to the positive/negative

output. Therefore, if a capacitor bypasses the SETP/SETN pin

resistor, the positive/negative output noise is independent of the

programmed positive/negative output voltage. The resultant positive

output noise is set just by the noise of the error amplifier of the

positive regulator, typically 2 nV/√Hz from a 10 kHz to 1 MHz

bandwidth and 0.8 μV rms from a 10 Hz to 100 kHz bandwidth

using a 4.7 μF SETP pin capacitor. The resultant negative output

noise is set just by the noise of the error amplifier of the negative

regulator, typically 2.2 nV/√Hz from a 10 kHz to 1 MHz bandwidth

and 0.8 μV rms from a 10 Hz to 100 kHz bandwidth using a 4.7 μF

SETN pin capacitor.

See the Figure 92, Figure 93, Figure 94, Figure 95, Figure 98,

Figure 99, Figure 102, Figure 103, Figure 106, and Figure 107

for the noise spectral density (for the 10 Hz to 10 MHz frequency

range and for the 0.1 Hz to 10 Hz 1/f noise frequency range)

and RMS integrated noise over various load currents and SET pin

capacitance information.

SETP/SETN PIN (BYPASS) CAPACITANCE:

NOISE, PSRR, TRANSIENT RESPONSE, AND

SOFT-START

In addition to reducing output noise, using a SETP/SETN pin

bypass capacitor also improves PSRR and transient performance.

Note that any bypass-capacitor leakage deteriorates the DC regula-

tion of the LT3097. Capacitor leakage of even 100 nA is a 0.1% DC

error. Therefore, Analog Devices, Inc., recommends using a good

quality, low-leakage ceramic capacitor.

Using a SETP/SETN pin bypass capacitor also soft starts the

output and limits inrush current. The RC time constant, formed by

the SETP/SETN pin resistor and capacitor, controls the soft-start

time. The ramp-up rate from 0% to 90% of nominal VOUT is the

following:

tSS≈2.3×RSET×CSET Fast Start−Up

Disabled

(1)

FAST STARTUP

For ultra-low noise applications that require low 1/f noise (that is, at

frequencies below 100 Hz), a larger value, SETP/SETN pin capaci-

tor is required of up to 22 μF. Typically, this larger value significantly

increases the start-up time of the regulator. However, the LT3097

incorporates fast start-up circuitry that increases the SETP/SETN

pin current to approximately 2 mA/1.8 mA during startup.

As shown in the Figure 122/Figure 123, the 2 mA/1.8 mA current

source remains engaged while PGFBP/PGFBN is less than 300

mV/-300 mV, unless the regulator is in current limit, dropout, ther-

mal shutdown, or the input voltage is less than the minimum VINP/

VINN.

If the fast start-up capability is not used, connect PGFBP/PGFBN

to INP/INN or to OUTP/OUTN for output voltages more than 300

mV/-300 mV, and note that this also disables the power-good

functionality.

See the Positive Regulator Programmable Power Good and Nega-

tive Regulator Programmable Power Good sections for more infor-

mation.

ENP/UVP

The ENP/UVP pin is used to put the positive regulator into a

micropower shutdown state. The positive regulator of the LT3097

has an accurate 1.24 V turn-on threshold on the ENP/UVP pin

with 130 mV of hysteresis. This threshold can be used with a

resistor-divider from the positive input supply to define an accurate

UVLO threshold for the positive regulator, as shown in the Figure

131. The ENP/UVP pin current (IENP/UVP) at the threshold from

Table 1 must be considered when calculating the resistor-divider

network as follows:

VINP UVLO =1.24 V× 1+RENP2RENP1

+IENP/UVP×RENP2

(2)

Where:

RENP1 and RENP2 are the resistors from the ENP/UVP pin to GND

and the ENP/UVP pin to INP, respectively.

IENP/UVP can be ignored if RENP1 is less than 100 kΩ. If unused,

connect the ENP/UVP pin to INP.

ENN/UVN

The ENN/UVN pin is used to put the negative regulator into a

micropower shutdown state. The negative regulator of the LT3097

has an accurate -1.26 V turn-on threshold on the ENN/UVN pin with

215 mV of hysteresis. This threshold can be used with a resistor-di-

vider from the negative input supply to define an accurate UVLO

ADM7151 Datasheet(PDF) 38 Page - Analog Devices

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