80C554 datasheet(12/76 Pages) PHILIPS

12 / 76 page

Philips Semiconductors

Preliminary specification

80C554/83C554/87C554

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM,

capture/compare, high I/O, 64L LQFP

2000 Nov 10

ERAM

256 BYTES

UPPER

128 BYTES

INTERNAL RAM

LOWER

128 BYTES

INTERNAL RAM

SPECIAL

FUNCTION

EXTERNAL

DATA

MEMORY

FFFF

0000

0100

SU00980

Figure 5. Internal and External Data Memory Address Space with EXTRAM = 0

Dual DPTR

The dual DPTR structure (see Figure 6) is a way by which the chip

will specify the address of an external data memory location. There

are two 16-bit DPTR registers that address the external memory,

and a single bit called DPS = AUXR1/bit0 that allows the program

code to switch between them.

The DPS bit status should be saved by software when switching

between DPTR0 and DPTR1.

DPS

DPTR1

DPTR0

DPH

(83H)

DPL

(82H)

EXTERNAL

DATA

MEMORY

SU00745A

BIT0

AUXR1

Figure 6.

Note that bit 2 is not writable and is always read as a zero. This

allows the DPS bit to be quickly toggled simply by executing an

INC AUXR1 instruction without affecting the other bits.

DPTR Instructions

The instructions that refer to DPTR refer to the data pointer that is

currently selected using the AUXR1/bit 0 register. The six

instructions that use the DPTR are as follows:

INC DPTR

Increments the data pointer by 1

MOV DPTR, #data16

Loads the DPTR with a 16-bit constant

MOV A, @ A+DPTR

Move code byte relative to DPTR to ACC

MOVX A, @ DPTR

Move external RAM (16-bit address) to

ACC

MOVX @ DPTR , A

Move ACC to external RAM (16-bit

address)

JMP @ A + DPTR

Jump indirect relative to DPTR

The data pointer can be accessed on a byte-by-byte basis by

specifying the low or high byte in an instruction which accesses the

SFRs. See application note AN458 for more details.

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