80C554 datasheet(24/76 Pages) PHILIPS

24 / 76 page

Philips Semiconductors

Preliminary specification

80C554/83C554/87C554

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM,

capture/compare, high I/O, 64L LQFP

2000 Nov 10

SUCCESSIVE

APPROXIMATION

CONTROL LOGIC

SUCCESSIVE

APPROXIMATION

DAC

–

START

STOP

Vin

VDAC

t/tau

VDAC

FULL SCALE

Vin

1/2

3/4

7/8

15/16

29/32

59/64

SU00958

Figure 21. Successive Approximation ADC

The low-to-high transition of STADC is recognized at the end of a

machine cycle, and the conversion commences at the beginning of

the next cycle. When a conversion is initiated by software, the

conversion starts at the beginning of the machine cycle which

follows the instruction that sets ADCS. ADCS is actually

implemented with two flip-flops: a command flip-flop which is

affected by set operations, and a status flag which is accessed

during read operations.

The next two machine cycles are used to initiate the converter. At

the end of the first cycle, the ADCS status flag is set and a value of

“1” will be returned if the ADCS flag is read while the conversion is in

progress. Sampling of the analog input commences at the end of the

second cycle.

During the next eight machine cycles, the voltage at the previously

selected pin of port 5 is sampled, and this input voltage should be

stable in order to obtain a useful sample. In any event, the input

voltage slew rate must be less than 10 V/ms in order to prevent an

undefined result.

The successive approximation control logic first sets the most

significant bit and clears all other bits in the successive

approximation register (10 0000 0000B). The output of the DAC

(50% full scale) is compared to the input voltage Vin. If the input

voltage is greater than VDAC, then the bit remains set; otherwise it

is cleared.

The successive approximation control logic now sets the next most

significant bit (11 0000 0000B or 01 0000 0000B, depending on the

previous result), and VDAC is compared to Vin again. If the input

voltage is greater than VDAC, then the bit being tested remains set;

otherwise the bit being tested is cleared. This process is repeated

until all ten bits have been tested, at which stage the result of the

conversion is held in the successive approximation register.

Figure 22 shows a conversion flow chart. The bit pointer identifies

the bit under test. The conversion takes four machine cycles per bit.

The end of the 10-bit conversion is flagged by control bit ADCON.4

(ADCI). The upper 8 bits of the result are held in special function

(ADC.1) and ADCON.6 (ADC.0). The user may ignore the two least

significant bits in ADCON and use the ADC as an 8-bit converter (8

upper bits in ADCH). In any event, the total actual conversion time is

50 machine cycles for the 8xC554. ADCI will be set and the ADCS

status flag will be reset 50 cycles after the command flip-flop

(ADCS) is set.

Control bits ADCON.0, ADCON.1, and ADCON.2 are used to control

an analog multiplexer which selects one of seven analog channels

(see Figure 23). An ADC conversion in progress is unaffected by an

external or software ADC start. The result of a completed

conversion remains unaffected provided ADCI = logic 1; a new ADC

conversion already in progress is aborted when the idle or

power-down mode is entered. The result of a completed conversion

(ADCI = logic 1) remains unaffected when entering the idle mode.

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