80C554 datasheet(18/76 Pages) PHILIPS

18 / 76 page

Philips Semiconductors

Preliminary specification

80C554/83C554/87C554

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM,

capture/compare, high I/O, 64L LQFP

2000 Nov 10

INT

CT0

CT1

CT2

CT3

CTI0

INT

CT0I

CTI1

CT1I

CTI2

CT2I

CTI3

CT3I

1/6

Prescaler

T2 Counter

8-bit overflow interrupt

16-bit overflow interrupt

External reset

enable

off

fosc

RT2

T2ER

COMP

CMO (S)

INT

COMP

CM1 (R)

INT

COMP

CM2 (T)

INT

P4.0

P4.1

P4.2

P4.3

P4.4

P4.5

P4.6

P4.7

STE

RTE

I/O port 4

set

reset

toggle

TG =

toggle status

INT

TML2

lower 8 bits

TMH2

higher 8 bits

T2 SFR address:

SU01447

Figure 13. Block Diagram of Timer 2

Capture Logic: The four 16-bit capture registers that Timer T2 is

connected to are: CT0, CT1, CT2, and CT3. These registers are

loaded with the contents of Timer T2, and an interrupt is requested

upon receipt of the input signals CT0I, CT1I, CT2I, or CT3I. These

input signals are shared with port 1. The four interrupt flags are in

the Timer T2 interrupt register (TM2IR special function register). If

the capture facility is not required, these inputs can be regarded as

additional external interrupt inputs.

Using the capture control register CTCON (see Figure 14), these

inputs may capture on a rising edge, a falling edge, or on either a

rising or falling edge. The inputs are sampled during S1P1 of each

cycle. When a selected edge is detected, the contents of Timer T2

are captured at the end of the cycle.

Measuring Time Intervals Using Capture Registers: When a

recurring external event is represented in the form of rising or falling

edges on one of the four capture pins, the time between two events

can be measured using Timer T2 and a capture register. When an

event occurs, the contents of Timer T2 are copied into the relevant

capture register and an interrupt request is generated. The interrupt

service routine may then compute the interval time if it knows the

previous contents of Timer T2 when the last event occurred. With a

12 MHz oscillator, Timer T2 can be programmed to overflow every

524 ms. When event interval times are shorter than this, computing

the interval time is simple, and the interrupt service routine is short.

For longer interval times, the Timer T2 extension routine may be

used.

Compare Logic: Each time Timer T2 is incremented, the contents

of the three 16-bit compare registers CM0, CM1, and CM2 are

compared with the new counter value of Timer T2. When a match is

found, the corresponding interrupt flag in TM2IR is set at the end of

the following cycle. When a match with CM0 occurs, the controller

sets bits 0-5 of port 4 if the corresponding bits of the set enable

80C554 Datasheet(PDF) 18 Page - NXP Semiconductors

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