ERTEC datasheet(34/51 Pages) RENESAS

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Data Sheet A17989EE2V0DS00

µPD800261

2.4 AC Characteristics

2.4.1 Clock timing

TA = -40 to +85°C, VDDCore = 1.35 V ~ 1.65 V, VDDIO = 3.0 V ~ 3.6 V

Table 2-4: Clock AC Characteristics

Parameter

Symbol

MIN.

TYP.

MAX.

Unit

Processor clock frequencyNote 1

PFC

50/100/

150

MHz

Processor clock periodNote 1

PTC

20/10/

6.66

Oscillator clock frequency

PLL_FC

- 50 ppm

+ 50 ppm

MHz

Reference clock frequency

REF_PLL_FC

- 50 ppm

+ 50 ppm

MHz

JTAGClk frequency

JTAG_FC

MHz

JTAGClk period

JTAG_TC

100

SPI1_SCLKIN frequency (slave mode)

SPI1_S_FC

4.16

MHz

SPI1_SCLKIN low time (slave mode)

SPI1_S_TCL

120

SPI1_SCLKIN high time (slave mode)

SPI1_S_TCH

120

SPI1_SCLKOUT frequency

(master mode)

SPI1_M_FC

769 x 10-6

MHz

SPI1_SCLKOUT period (master mode)

SPI1_M_TC

1.3 x 106

SPI1_SCLKOUT low time

(master mode)Note 2

SPI1_M_TCL

SPI1_SCLKOUT high time

(master mode)Note 2

SPI1_M_TCH

CLK_SDRAM frequency

SDRAM_FC

MHz

CLK_SDRAM period

SDRAM_TC

CLK_SDRAM clock stability

SDRAM_TCS

+/- 0.2

CLK_SDRAM input high timeNote 2

SDRAM_TCH

CLK_SDRAM input low timeNote 2

SDRAM_TCL

Notes: 1. The actually permitted maximum clock frequency respectively minimum clock period is given by the

CONFIG(4:3) pin setting during reset and depends additionally on the accuracy of the oscillator

clock.

2. High time and low time are specified in per cent of the nominal clock period.

ERTEC Datasheet(PDF) 34 Page - Renesas Technology Corp

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