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ERTEC Datasheet(PDF) 44 Page - Renesas Technology Corp |
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ERTEC Datasheet(HTML) 44 Page - Renesas Technology Corp |
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44 / 51 page ![]() 44 Data Sheet A17989EE2V0DS00 µPD800261 (2) SPI interface configured to master mode TA = -40 to +85°C, VDDCore = 1.35 V ~ 1.65 V, VDDIO = 3.0 V ~ 3.6 V Figure 2-9: SPI Timing in Master Mode (TI-format Example) Table 2-11: SPI Timing Specifications (master mode) Parameter Symbol Condition MIN. MAX. Unit SPI1_SSPRXD setup time tSSPRXDS -14 - ns SPI1_SSPRXD hold time tSSPRXDH -0 - ns SPI1_SFRMOUT delay time tSFRMOUTD --0.3 0.3 ns SPI1_SSPTXD delay tSSPTXDD --0.6 0.1 ns SPI1_SSPOE delay tSSPOED --0.6 0.1 ns SPI1_SSPCTLOE delay tSSPCTLOED --0.7 0 ns |
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