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Data Sheet A17989EE2V0DS00

µPD800261

TDONote 6

O-

SRST_N

I/O

50 k

Ω pull up

TAP_SEL

50 k

Ω pull up

Notes: 1. These pins are used as inputs only during the active reset phase. The levels during reset shown in

Table 1-15 refer to the default configuration without external pull-up/down resistors connected to

BOOT(3:0) and CONFIG(6:1)

2. These pins have alternative functions, to which the pin characteristics apply as well. Note that the I/O

type given in Table 1-15 applies to the pin. I/O types that apply to one of the shared functions of a

specific pin are found in Tables 1-1 to 1-12.

3. The reset behaviour of this pin is determined by the CONFIG1 signal.

4. RESET_N must be externally driven low in order to reset the device.

5. High level is generated from external pull up resistor and not by internal device circuitry.

6. The reset signal, that affects these signals, is TRST_N.

7. All trace interface pins are configured as inputs in the default configuration that is determined by the

internal pull-up/down resistors at the CONFIG(6:5) and CONFIG1 pins.

Remarks: 1. Shared pins are not listed with all possible pin names. Please check Tables 1-1 to 1-11 for possi-

ble pin names first, before looking up reset characteristics and recommended connections in

Table 1-15.

2. I/O and level during reset are given for the default configuration that is determined by the internal

pull-up/down resistors at the CONFIG(6:5) and CONFIG1 pins.

Table 1-15:

Pin Status During Reset and Recommended Connections (2/2)

Pin Name

I/O

Internal pull

up/down

I/O during

reset

Level

during reset

External pull

up/down required

ERTEC Datasheet(PDF) 27 Page - Renesas Technology Corp