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ERTEC Datasheet(PDF) 43 Page - Renesas Technology Corp |
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ERTEC Datasheet(HTML) 43 Page - Renesas Technology Corp |
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43 / 51 page ![]() 43 Data Sheet A17989EE2V0DS00 µPD800261 2.4.4 SPI timing specifications Remarks: 1. Please note, that different serial clock frequency ranges for SPI slave and master modes are given in Table 2-4. 2. Timing diagrams are shown for TI-format only. Other transfer formats can be configured, however the AC-timing parameters (setup/hold times, delays) remain in principle unchanged. 3. Not every external SPI device, that is connected to ERTEC 200, requires usage of all available SPI signals. (1) SPI interface configured to slave mode TA = -40 to +85°C, VDDCore = 1.35 V ~ 1.65 V, VDDIO = 3.0 V ~ 3.6 V Figure 2-8: SPI Timing in Slave Mode (TI-format Example) Table 2-10: SPI Timing Specifications (slave mode) Parameter Symbol Condition MIN. MAX. Unit SPI1_SSPRXD setup time tSSPRXDS -20 - ns SPI1_SSPRXD hold time tSSPRXDH -60 - ns SPI1_SFRMIN setup time tSFRMINS -40 - ns SPI1_SFRMIN hold time tSFRMINH -20 - ns SPI1_SSPTXD delay tSSPTXDD - - 40 ns SPI1_SSPOE delay tSSPOED - - 40 ns |
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