ERTEC datasheet(41/51 Pages) RENESAS

41 / 51 page

Data Sheet A17989EE2V0DS00

µPD800261

(3)

LBU Read from ERTEC 200 with Common Read/Write line (LBU_RDY_N active low)

TA = -40 to +85°C, VDDCore = 1.35 V ~ 1.65 V, VDDIO = 3.0 V ~ 3.6 V

Figure 2-6:

LBU Read from ERTEC 200 with Common Read/Write line

Table 2-8: LBU Read from ERTEC 200 with Common Read/Write line

Parameter

Symbol

Condition

MIN.

MAX.

Unit

Write signal deasserted to chip select

asserted setup time

tWCS

-2

Address valid to chip select asserted

setup time

tACS

-0

Chip select asserted to ready enabled

delay

tCRE

Chip select asserted to data enable

delay

tCDE

Ready active pulse width

tRAP

-17

Ready asserted to data valid delay

tRTD

Write signal inactive to chip select deas-

serted hold time

tCWH

-0

Address valid to chip select deasserted

hold time

tCAH

-0

Data valid/enabled to chip select deas-

serted hold time

tCDH

Read recovery time

tRR

-25

LBU_CS_R_N/

LBU_CS_M_N

LBU_WR_N

LBU_A(20:0)/

LBU_SEG(1:0)/

LBU_BE(1:0)_N

LBU_RDY_N

LBU_D(15:0)

ACS

WCS

CRE

CDE

RAP

RTD

CDH

CAH

CWH

ERTEC Datasheet(PDF) 41 Page - Renesas Technology Corp

ERTEC Datasheet(HTML) 41 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

Datasheet Download

Link URL