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ERTEC Datasheet(PDF) 36 Page - Renesas Technology Corp |
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ERTEC Datasheet(HTML) 36 Page - Renesas Technology Corp |
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36 / 51 page ![]() 36 Data Sheet A17989EE2V0DS00 µPD800261 2.4.2 I/O timing specifications TA = -40 to +85°C, VDDCore = 1.35 V ~ 1.65 V, VDDIO = 3.0 V ~ 3.6 V Table 2-5: I/O Timing Specifications Signal Input Output Unit Clock Notes Setup time TIS min. Hold time TIH min. Valid delay TOV max. Hold time TOH min. D(31:0) 10 0 12.5 2 ns CLK_SDRAM 4 A(23:0) 11 2 ns CLK_SDRAM 4 BE(3:0)_DQM_N(3:0) 11 2 ns CLK_SDRAM 4 CAS_SDRAM_N 11 2 ns CLK_SDRAM 5 RAS_SDRAM_N 11 2 ns CLK_SDRAM 5 WE_SDRAM_N 11 2 ns CLK_SDRAM 5 CS_SDRAM_N 11 2 ns CLK_SDRAM 5 WR_N 11 2 ns CLK_SDRAM 4 RD_N 11 2 ns CLK_SDRAM 4 LBU_D(15:0) 10.4 0.5 9.2 1 ns 50 MHz 4 LBU_A(20:16) 10.4 0.5 9.2 1 ns 50 MHz 2 LBU_A(15:0) 10.4 0.5 9.2 1 ns 50 MHz 3 LBU_RDY_N 10.4 0.5 9.2 1 ns 50 MHz 5 LBU_IRQ(1:0)_N 10.4 0.5 9.2 1 ns 50 MHz 5 LBU_SEG(1:0)_N 10.4 0.5 9.2 1 ns 50 MHz 2 LBU_CS_M_N 10.4 0.5 9.2 1 ns 50 MHz 2 LBU_CS_R_N 10.4 0.5 9.2 1 ns 50 MHz 2 LBU_WR_N 10.4 0.5 9.2 1 ns 50 MHz 3 LBU_RD_N 10.4 0.5 9.2 1 ns 50 MHz 3 LBU_BE(1:0)_N 10.4 0.5 9.2 1 ns 50 MHz 3 TDI 8 0 ns TCK - TMS 8 0 ns TCK - TDI 8 0 ns TCK - TMS 8 0 ns TCK - TDO 10 2 ns TCK 5 TRACESYNC Tc - 3 2 ns TRACECLK 1, 3 PIPESTA(2:0) Tc - 3 2 ns TRACECLK 1, 3 TRACEPKT Tc - 3 2 ns TRACECLK 1, 3 Notes: 1. If the trace interface is operated in half rate mode, Tc corresponds to the distance between a rising and the subsequent falling edge of TRACECLK; if the trace interface is operated in full rate mode, Tc corresponds to a full period of the trace clock TRACECLK. 2. Minimum hold time is measured with 10 pF load and maximum valid delay is measured with 25 pF load. 3. Minimum hold time is measured with 10 pF load and maximum valid delay is measured with 10 pF load. 4. Minimum hold time is measured with 10 pF load and maximum valid delay is measured with 50 pF load. 5. Minimum hold time is measured with 10 pF load and maximum valid delay is measured with 30 pF load |
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