ERTEC datasheet(25/51 Pages) RENESAS

25 / 51 page

Data Sheet A17989EE2V0DS00

µPD800261

F_CLK

3.3 V CMOS

REF_CLK

3.3 V CMOS

6 mA

RESET_N

Schmitt

50 k

Ω pull up

P(2:1)TxN

I/O

Analog

P(2:1)TxP

I/O

Analog

P(2:1)TDxN Note 3

3.3 V CMOS

12 mA

P(2:1)TDxP Note 3

3.3 V CMOS

12 mA

P(2:1)RxN

I/O

Analog

P(2:1)RxP

I/O

Analog

P(2:1)RDxN

PECL

P(2:1)RDxP

PECL

P(2:1)SDxN

PECL

P(2:1)SDxP

PECL

EXTRES

I/O

Analog

TRST_N

Schmitt

TCK

Schmitt

50 k

Ω pull up

TDI

Schmitt

50 k

Ω pull up

TMS

Schmitt

50 k

Ω pull up

TDO

3.3 V CMOS

6 mA

SRST_N

I/O

Schmitt

3.3 V CMOS

50 k

Ω pull up

6 mA

TAP_SEL

Schmitt

50 k

Ω pull up

Notes: 1. The address pins A(23:15) and the DTR_N pin are used as inputs only during the active reset phase.

2. These pins have alternative functions, to which the pin characteristics apply as well. Note that the I/O

type given in Table 1-14 applies to the pin. I/O types that apply to one of the shared functions of a

specific pin are found in Tables 1-1 to 1-12.

3. These pins require external circuitry in order to provide PECL compliant output levels.

Remark:

Shared pins are not listed with all possible pin names. Please check Tables 1-1 to 1-11 for possible

pin names first, before looking up pin characteristics in Table 1-14.

Table 1-14:

Pin Characteristics (2/2)

Pin Name

I/O

Input type

Output type

Internal pull

up/down

Drive capability

IOH

IOL

ERTEC Datasheet(PDF) 25 Page - Renesas Technology Corp

ERTEC Datasheet(HTML) 25 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

Datasheet Download

Link URL