ERTEC datasheet(38/51 Pages) RENESAS

38 / 51 page

Data Sheet A17989EE2V0DS00

µPD800261

2.4.3 LBU timing specifications

Remarks: 1. The polarity of the LBU_RDY_N signal can be configured using the CONFIG6 pin.

LBU_POL_RDY signal. LBU_RDY_N must be pulled to its "ready" level by an external

pull-down or the internal pull-up resistor.

CONFIG6 = 0b

LBU_RDY_N active low

use external pull-down resistor

CONFIG6 = 1b

LBU_RDY_N active high

use internal pull-up resistor (default

setting)

2. The CONFIG5 signal is used to select access control through separate read/write lines

or a common read/write line.

CONFIG5 = 0b

use separate read/write lines LBU_RD_N and LBU_WR_N (default

setting)

CONFIG5 = 1b

use common read/write line LBU_WR_N

In case of a common read/write line, LBU_WR_N must be high for a read access and

low for a write access. The unused LBU_RD_N input can then be left open because it is

pulled to inactive (high) level by an internal pull-up resistor.

3. ERTEC 200 responds to a read or write access by first driving LBU_RDY_N to "not

ready" level. Then LBU_RDY_N is driven to "ready" level for tRAP.. The length of the "not

ready" phase of LBU_RDY_N varies strongly on the internal states of ERTEC 200 and

the currently ongoing internal communication processes. Therefore no upper limit for

the length of the "not ready" period is specified.

4. ERTEC 200 has two LBU chip select inputs; one for access to the page configuration

registers (LBU_CS_R_N) and one to access to the ERTEC 200 memory addess space

(LBU_CS_M_N). Only one of these chip select signals may be active at a time and it is

not allowed to change the chip select during the complete access.

ERTEC Datasheet(PDF) 38 Page - Renesas Technology Corp