AD7294 datasheet(6/45 Pages) AD

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AD7294

Preliminary Technical Data

Rev. PrB | Page 6 of 45

TIMING CHARACTERISTICS1,2

I2C Serial Interface

DVDD = 4.5 V to 5.5 V, AGND = DGND = 0 V. All specifications TMIN to TMAX, unless otherwise noted.

Table 2.

Parameter

Limit at TMIN, TMAX

Unit

Description

FSCL

400

kHz max

SCL clock frequency

2.5

µs min

SCL cycle time

0.6

µs min

tHIGH, SCL high time

1.3

µs min

tLOW, SCL low time

0.6

µs min

tHD,STA, start/repeated start condition hold time

100

ns min

tSU,DAT, data set-up time

t63

0.9

µs max

tHD,DAT, data hold time

µs min

tHD,DAT, data hold time

0.6

µs min

tSU,STA, set-up time for repeated start

0.6

µs min

tSU,STO, stop condition set-up time

1.3

µs min

tBUF, bus free time between a stop and a start condition

t10

300

ns max

tR, rise time of SCL and SDA when receiving

ns min

tR, rise time of SCL and SDA when receiving (CMOS compatible)

t11

300

ns max

tF, fall time of SDA when transmitting

ns min

tF, fall time of SDA when receiving (CMOS compatible)

300

ns max

tF, fall time of SCL and SDA when receiving

20 + 0.1Cb4

ns min

tF, fall time of SCL and SDA when transmitting

400

pF max

Capacitive load for each bus line

1 Guaranteed by design and characterization; not subject to production test.

2 See Figure 2.

3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of SCL’s falling edge.

4 Cb is the total capacitance in pF of one bus line. tR and tF are measured between 0.3 DVDD and 0.7 DVDD.

START

CONDITION

REPEATED

START

CONDITION

STOP

CONDITION

t11

t10

SDA

SCL

Figure 2. I2C-Compatible Serial Interface Timing Diagram

50pF

TO OUTPUT PIN

VOH (MIN) OR

VOL (MAX)

200

µA

200

µA

IOL

IOH

Figure 3. Load Circuit for Digital Output

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