AD7294 datasheet(28/45 Pages) AD

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AD7294

Preliminary Technical Data

Rev. PrB | Page 28 of 45

SAMPLE DELAY AND BIT TRIAL DELAY

It is recommended that no I2C Bus activity occurs when a

conversion is taking place; however, this may not be possible,

for example when operating in automatic cycle mode. To

maintain the performance of the ADC in such cases, Bits D14

and D13 in the configuration register are used to delay critical

sample intervals and bit trials from occurring while there is

activity on the I2C bus. This may increase the conversion time.

When Bits D14 and D13 are both 1, the bit trial-and-sample

interval delaying mechanism are implemented. The default

setting of D14 and D13 is 0. If bit trial delays extend longer than

1 µs, the conversion terminates. When D14 is 1, the sampling

instant delay is implemented. When D13 is 1, the bit trial delay

is implemented. To turn off both the sample delay and bit trial

delay, set D14 and D13 to 0.

POWER-DOWN REGISTER

The power-down register is an 8-bit read/write register that is

used to power down various sections on the AD7294 device.

Table 19. Power-Down Register Description

Bit

Function

Power down full chip (apart from DACs)

Reserved

Power down ADC reference buffer (to allow

external reference, 1 at power-up)

Power down DAC reference buffer (to allow

external reference, 1 at power-up)

Power down temperature sensor

Power down ISENSE2

Power down ISENSE1

DAC outputs set to high impedance (set

automatically if die temperature >150°C)

DATAHIGH/DATALOW REGISTER

The DATAHIGH / DATALOW registers for a channel are 16-bit,

read/write registers. General alert is flagged by the MSB, D15.

D14 – D12 are not used in the register and are read as 0s. The

remaining 12-bits set the high/low limits for the relevant

channel. With respect to Channels 1 to 4, for Single Ended

mode, 000 and FFF are the defaults values. For differential

mode on Channels 1 to 4, the default values for DATAHIGH &

DATALOW are 7FF and 800. Note that if the part is configured in

Single Ended mode and the limits are changed, the user must

re-program limits when changing to a different mode.

Channels 5 and 6 ( ISENSE1 and ISENSE2 ) are two’s complement

format and so the default limits will also be 7FF and 800. There

is no differential mode for channels 5 and 6.

Channels 7 to 9, (TSENSE1, TSENSE2 and TSENSEINT) default to 3FF

and 400 for the DATAHIGH and DATALOW limits as they are in

two’s complement 10-bit format. Differential mode is not

available for channels 7 to 9. The AD7294 signals an alert (in

either hardware, software or both, depending on the

configuration) if the result moves outside the upper or lower

limit set by the user.

Table 20. Default values for DATAHIGH and DATALOW

REGISTERS

ADC

Channel

Single Ended

Differential

CH1

000 and FFF

7FF and 800

CH2

000 and FFF

7FF and 800

CH3

000 and FFF

7FF and 800

CH4

000 and FFF

7FF and 800

ISENSE1

7FF and 800 (2’s

Complement)

N/A

ISENSE2

7FF and 800 (2’s

Complement)

N/A

TSENSE1

3FF and 400 (2’s

Complement)

N/A

TSENSE2

3FF and 400 (2’s

Complement)

N/A

TSENSEINT

3FF and 400 (2’s

Complement)

N/A

The DATAHIGH register stores the upper limit that activates the

ALERT output and/or the Alert_Flag bit in the conversion

result register. If the value in the conversion result register is

greater than the value in the DATAHIGH register, an alert occurs.

When the conversion result returns to a value of at least N LSB

below the DATAHIGH register value, the ALERT output pin and

Alert_Flag bit are reset. The value of N is taken from the 12-bit

hysteresis register associated with that channel. For the TSENSE

limit registers D11 is equal to 0, as this denotes the diode open-

circuit flag in the TSENSE registers.

The DATALOW register stores the lower limit that activates the

ALERT output and/or the Alert_Flag bit in the conversion

result register. If the value in the conversion result register is less

than the value in the DATALOW register, an alert occurs. When

the conversion result returns to a value of at least N LSB above

the DATALOW register value, the ALERT output pin and

Alert_Flag bit are reset. The value of N is taken from the

hysteresis register associated with that channel.

The ALERT pin can also be reset by writing to Bits D2 and D1

in the configuration register.

Table 21. AD7294 DATAHIGH/LOW Register (First R/W)

MSB

LSB

D15

D14

D13

D12

D11

D10

Alert_Flag

B11

B10

Table 22. AD7294 DATAHIGH/LOW Register (Second R/W)

MSB

LSB

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