AD7294 datasheet(26/45 Pages) AD

26 / 45 page

AD7294

Preliminary Technical Data

Rev. PrB | Page 26 of 45

TSENSE1, TSENSE2 RESULT REGISTERS

Registers TSENSE1 and TSENSE2 are 16-bit read/write registers.

General alert is flagged by the MSB, D15. Bits D14 to D12 are

reserved for the ADC channel allocation. D11 is reserved for

flagging diode open-circuits. The temperature reading from the

ADC is stored in a 10-bit twos complement format plus a sign

bit, D10 to D0. Writing to the TSENSE1 register sets the DAC2

output code while writing to the TSENSE2 register sets the DAC3

output code.

TSENSEINT RESULT REGISTER

The TSENSEINT register is a 16-bit read/write register used to

store the ADC data generated from the internal temperature

sensor. Similar to the TSENSE1 and TSENSE2 result registers, this

10-bit twos complement format and in a sign bit format, D10 to

D0, and uses the MSB as a general alert flag. However, Bits D14

to D11 are not used. Conversions take place approximately every

5 ms. Writing to this register sets the DAC4 output code. The

temperature data format in Table 6 also applies to the internal

temperature sensor data.

TSENSE OFFSET REGISTERS

Due to the high frequency clock signals of the system, some

temperature errors can be attributable to noise coupled onto the

D+/D− lines of the remote temperature sensors even when the

layout guidelines are followed. Constant high frequency noise

usually attenuates/increases the temperature measurements by a

linear constant value. The AD7294 has temperature offset 8-bit

twos complement registers for both Remote Channels TSENSE1

and TSENSE2. By completing a one-time calibration of the system,

the user can determine the offset caused by system board noise

and null it using the offset registers. The offset registers for

TSENSE1 and TSENSE2 are 8-bit read/write registers that store data

in a twos complement format. This data is subtracted from the

temperature readings taken by TSENSE1 and TSENSE2 temperature

sensors. The offset is carried out before the values are stored in

the TSENSE result register.

Table 12. TSENSE Offset Data Format

Digital Input

Bit Weight ( °C )

1111 1111

− 0.25

1000 0000

− 32

0111 1111

+ 31.75

0000 0000

+ 0.0

ALERT STATUS REGISTERS

The alert status registers are 8-bit read/write registers that

provides information on an alert event. If a conversion results in

activating the ALERT pin or Alert_Flag bit in the result register

or TSENSE registers, the alert status register can be read to gain

further information.

status bits per channel, one corresponding to each of the

DATAHIGH and DATALOW limits. It stores the alert event data for

Channels 1 to 4, which are the standard voltage inputs. The bit

with a status of 1 shows where the violation occurred—that is,

on which channel—and whether the violation occurred on the

upper or lower limit. If a second alert event occurs on another

channel between receiving the first alert and interrogating the

alert status register, the corresponding bit for that alert event is

also set.

consists of three channels with two status bits per channel,

representing the specified DATAHIGH and DATALOW limits. Bits B3

to B0 correspond to the high and low limit alerts for the current

sense inputs. Bits B5 to B4 represent the ISENSE over the full-scale

range of 200 mV.

user if an open diode flag occurs on the external temperature

sensors. An over temperature alert for the external temperature

sensor occupies C6. The remaining 6 bits in this register are

used to store alert event data for TSENSE1, TSENSE2 and TSENSEINT

with two status bits per channel, one corresponding to each of the

DATAHIGH and DATALOW limits.

The entire contents of the alert status register can be cleared by

writing 1 to bit D1 and 1 to bit D2 in the configuration register,

as shown in Table 17. This can also be achieved by writing all 1s

to the alert status register itself. Therefore, if the alert status

contents of the alert status register are cleared or reset to all 0s.

CHANNEL SEQUENCE REGISTER

The channel sequence register is an 8-bit read/write register that

allows the user to sequence the ADC conversions in autocycle

mode. This mode must first be selected in the configuration

example, when checking for alerts on a channel. On power-up,

the channel sequence register contains all 0s, thus disabling

automatic cycle operation of the AD7294. To enable the

automatic cycle mode, the user must write a 1 to the desired

channel.

The temperature sense channels, including TSENSEINT, are a

special case. The conversions on these channels take place

automatically, unless the temperature sense circuit is powered

down, either after certain other conversions or in other quiet

times. This is transparent to the user.

CONFIGURATION REGISTER

The configuration register is a 16-bit read/write register that is

used to set the operating modes of the AD7294. The bit

functions of the configuration register are outlined in. Table 17

AD7294 Datasheet(PDF) 26 Page - Analog Devices

AD7294 Datasheet(HTML) 26 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

Datasheet Download

Link URL