AD7294 datasheet(15/45 Pages) AD

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Preliminary Technical Data

AD7294

Rev. PrB | Page 15 of 45

Pseudodifferential Mode

The AD7294 can have two pseudodifferential pairs, see the

Configuration Register section for register details.

Uncommitted input channels 1 and 2 are a pseudodifferential

pair, as are channels 3 and channel 4 . In this mode, VIN+ is

connected to the signal source, which must have amplitude of

VREF (or 2 × VREF, depending on the range chosen) to make use

of the full dynamic range of the part. A dc input is applied to

the VIN− pin. The voltage applied to this input provides an offset

from ground or a pseudoground for the VIN+ input. Which

channel is VIN+ is determined by the ADC channel allocation.

The differential mode must be selected in order to operate in the

pseudodifferential mode. The resulting converted

pseudodifferential data is stored in 2s complement format in the

result register.

The governing equation for the pseudodifferential mode, for

channel 1 is:

VOUT = 2(VIN0 − VIN1) − VREF_ADC

Where VIN0 is the single-ended signal on channel 1 and VIN1 is

the single-ended signal on channel 2.

The benefit of pseudodifferential inputs is that they separate the

analog input signal ground from the ADC’s ground, allowing dc

common-mode voltages to be cancelled.

DIGITAL INPUTS

The digital inputs applied to the AD7294 are not limited by the

maximum ratings that limit the analog inputs. Instead, the digital

inputs can be applied at up to 7 V and are not restricted by the

VDD + 0.3 V limit as are the analog inputs, see the Absolute

Maximum Ratings section for more information. Another advan-

tage of the SDA, SCL, and A0 to A2 not being restricted by the

VDD + 0.3 V limit is that power supply sequencing issues are

avoided. If one of these digital inputs is applied before VDD,

there is no risk of latch-up, as there would be on the analog

inputs if a signal greater than 0.3 V were applied prior to VDD.

VDRIVE

The AD7294 also has a VDRIVE feature to control the voltage at

which the I2C interface operates. Because the I2C pins are open-

drain, there is not a corresponding VDD pin. The VDRIVE pin

should be connected to the supply that the I2C bus is pulled up

to. This is not a supply pin in I2C mode—it merely sets up the

input threshold levels. VDRIVE allows the ADC to easily interface

to both 3 V and 5 V processors. For example, if the AD7294 is

operated with a VDD of 5 V, the VDRIVE pin can be powered from

a 3 V supply, allowing a large dynamic range with low voltage

digital processors. Thus, the AD7294 can be used with the 2 ×

VREF input range with a VDD of 5 V while still being able to interface

to 3 V digital parts.

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