PowerPC 601 RISC Microprocessor Technical Summary

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word operand loads and stores between memory and a set of 32 general-purpose registers (GPRs). It also

provides for word and double-word operand loads and stores between memory and a set of 32 floating-point

registers (FPRs).

Computational instructions do not modify memory. To use a memory operand in a computation and then

modify the same or another memory location, the memory contents must be loaded into a register, modified,

and then written back to the target location with distinct instructions.

PowerPC processors follow the program flow when they are in the normal execution state. However, the

flow of instructions can be interrupted directly by the execution of an instruction or by an asynchronous

event. Either kind of exception may cause one of several components of the system software to be invoked.

3.3.1.2 Calculating Effective Addresses

The effective address (EA) is the 32-bit address computed by the processor when executing a memory

access or branch instruction or when fetching the next sequential instruction.

The PowerPC architecture supports two simple memory addressing modes:

•

EA = (rA|0) + offset (including offset = 0) (register indirect with immediate index)

•

EA = (rA|0) + rB (register indirect with index)

These simple addressing modes allow efficient address generation for memory accesses. Calculation of the

effective address for aligned transfers occurs in a single clock cycle.

For a memory access instruction, if the sum of the effective address and the operand length exceeds the

maximum effective address, the storage operand is considered to wrap around from the maximum effective

address to effective address 0.

Effective address computations for both data and instruction accesses use 32-bit unsigned binary arithmetic.

A carry from bit 0 is ignored in 32-bit implementations.

3.3.2 PowerPC 601 Microprocessor Instruction Set

The 601 instruction set is defined as follows:

•

The 601 implements the 32-bit PowerPC architecture instructions except as indicated in

Appendix C, “PowerPC Instructions Not Implemented,” in the PowerPC 601 RISC Microprocessor

User’s Manual. Otherwise, all instructions not implemented in the 601 are defined as optional in the

PowerPC architecture.

•

The 601 supports a number of POWER instructions that are otherwise not implemented in the

PowerPC architecture. These are listed in Appendix B, “POWER Architecture Cross Reference,”

and individual instructions are described in Chapter 10, “Instruction Set,” in the PowerPC 601 RISC

Microprocessor User’s Manual.

•

The 601 implements the External Control Input Word Indexed (eciwx) and External Control Output

Word Indexed (ecowx) instructions, which are optional in the PowerPC architecture definition.

•

Several of the instructions implemented in the 601 function somewhat differently than they are

defined in the PowerPC architecture. These differences typically stem from design differences; for

instance, the PowerPC architecture defines several cache control instructions specific to separate

instruction and data cache designs.

•

When executed on the 601, such instructions may provide a subset of the functions of the instruction

or they may be no-ops.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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