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PowerPC 601 RISC Microprocessor Technical Summary

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Data transfer termination signals—Data termination signals are required after each data beat in a

data transfer. In a single-beat transaction, the data termination signals also indicate the end of the

tenure, while in burst accesses, the data termination signals apply to individual beats and indicate

the end of the tenure only after the final data beat. They also indicate whether a condition exists

that requires the data phase to be repeated.

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System status signals—These signals include the interrupt signal, checkstop signals, and both soft-

and hard-reset signals. These signals are used to interrupt and, under various conditions, to reset the

processor.

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Processor state signals—These two signals are used to set the reservation coherency bit and set the

size of the 601’s output buffers.

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Miscellaneous signals—These signals provide information about the state of the reservation

coherency bit.

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COP interface signals—The common on-chip processor (COP) unit is the master clock control unit

and it provides a serial interface to the system for performing built-in self test (BIST).

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Test interface signals—These signals are used for internal testing.

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Clock signals—These signals determine the system clock frequency. These signals can also be used

to synchronize multiprocessor systems.

NOTE

A bar over a signal name indicates that the signal is active low—for

example, ARTRY (address retry) and TS (transfer start). Active-low

signals are referred to as asserted (active) when they are low and negated

when they are high. Signals that are not active-low, such as AP0–AP3

(address bus parity signals) and TT0–TT4 (transfer type signals) are

referred to as asserted when they are high and negated when they are low.

3.8.4 Signal Configuration

Figure 7 illustrates the 601 microprocessor's logical pin configuration, showing how the signals are grouped.

Freescale Semiconductor, Inc.

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