PowerPC 601 RISC Microprocessor Technical Summary

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Cache implementation—Section 3.4, “Cache Implementation,” describes the cache model that is

defined generally for PowerPC processors by the virtual environment architecture. It also provides

specific details about the 601 cache implementation.

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Exception model—Section 3.5, “Exception Model,” describes the exception model of the PowerPC

operating environment architecture and the differences in the 601 exception model.

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Memory management—Section 3.6, “Memory Management,” describes generally the conventions

for memory management among the PowerPC processors. This section also describes the general

differences between the 601 and the 32-bit PowerPC memory management specification.

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Instruction timing—Section 3.7, “Instruction Timing,” provides a general description of the

instruction timing provided by the superscalar, parallel execution supported by the PowerPC

architecture.

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System interface—Section 3.8, “System Interface,” describes the signals implemented on the 601.

3.1 Features

The 601 is a high-performance, superscalar PowerPC implementation. The PowerPC architecture allows

optimizing compilers to schedule instructions to maximize performance through efficient use of the

PowerPC instruction set and register model. The multiple, independent execution units allow compilers to

maximize parallelism and instruction throughput. Compilers that take advantage of the flexibility of the

PowerPC architecture can additionally optimize system performance of the PowerPC processors.

The 601 implements the PowerPC architecture, with the extensions and variances listed in Appendix H,

“Implementation Summary for Programmers,” in the PowerPC 601 RISC Microprocessor User’s Manual.

Specific features of the 601 are listed in Section 1.1, “PowerPC 601 Microprocessor Features.”

3.2 Registers and Programming Model

The following subsections describe the general features of the PowerPC registers and programming model

and of the specific 601 implementation, respectively.

3.2.1 PowerPC Registers and Programming Model

The PowerPC architecture defines register-to-register operations for most computational instructions.

Source operands for these instructions are accessed from the registers or are provided as immediate values

embedded in the instruction opcode. The three-register instruction format allows specification of a target

register distinct from the two source operands. Load and store instructions transfer data between registers

and memory.

PowerPC processors have two levels of privilege—supervisor mode of operation (typically used by the

operating environment) and one that corresponds to the user mode of operation (used by the application

software). The programming models incorporate 32 GPRs, 32 FPRs, special-purpose registers (SPRs), and

several miscellaneous registers. Note that there are several registers that are part of the PowerPC architecture

that are not implemented in the 601; for example, the time base registers are not implemented in the 601.

Likewise, each PowerPC implementation has its own unique set of hardware implementation (HID)

registers, which are implementation-specific.

This division allows the operating system to control the application environment (providing virtual memory

and protecting operating-system and critical machine resources). Instructions that control the state of the

processor, the address translation mechanism, and supervisor registers can be executed only when the

processor is operating in supervisor mode.

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