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PowerPC 601 RISC Microprocessor Technical Summary

Part 2 Levels of the PowerPC Architecture

The PowerPC architecture consists of the following layers, and adherence to the PowerPC architecture can

be measured in terms of which of the following levels of the architecture is implemented:

•

PowerPC user instruction set architecture—Defines the base user-level instruction set, user-level

registers, data types, floating-point exception model, memory models for a uniprocessor

environment, and programming model for uniprocessor environment.

•

PowerPC virtual environment architecture—Describes the memory model for a multiprocessor

environment, defines cache control instructions, and describes other aspects of virtual

environments. Implementations that conform to the PowerPC virtual environment architecture also

adhere to the PowerPC user instruction set architecture, but may not necessarily adhere to the

PowerPC operating environment architecture.

•

PowerPC operating environment architecture—Defines the memory management model,

supervisor-level registers, synchronization requirements, and the exception model.

Implementations that conform to the PowerPC operating environment architecture also adhere to

the PowerPC user instruction set architecture and the PowerPC virtual environment architecture

definition.

Note that while the 601 is said to adhere to the PowerPC architecture at all three levels, it diverges in aspects

of its implementation to a greater extent than should be expected of subsequent PowerPC processors. Many

of the differences result from the fact that the 601 design provides compatibility with an existing architecture

standard (POWER), while providing a reliable platform for hardware and software development compatible

with subsequent PowerPC processors.

Note that except for the POWER instructions and the RTC implementation, the differences between the 601

and the PowerPC architecture are primarily differences in the operating environment architecture.

The PowerPC architecture allows a wide range of designs for such features as cache and system interface

implementations.

Part 3 PowerPC 601 Microprocessor: Implementation

The PowerPC architecture is derived from the IBM Performance Optimized with Enhanced RISC

(POWER) architecture. The PowerPC architecture shares the benefits of the POWER architecture optimized

for single-chip implementations. The architecture design facilitates parallel instruction execution and is

scalable to take advantage of future technological gains. For compatibility, the 601 also implements

instructions from the POWER user programming model that are not part of the PowerPC definition.

Part 3, “PowerPC 601 Microprocessor: Implementation,” describes the PowerPC architecture in general,

noting where the 601 differs. The organization of Part 3 follows the sequence of the chapters in the PowerPC

601 RISC Microprocessor User’s Manual as follows:

•

Features—Section 3.1, “Features,” describes general features that the 601 shares with the PowerPC

family of microprocessors. It does not list PowerPC features not implemented in the 601.

•

Registers and programming model—Section 3.2, “Registers and Programming Model,” describes

the registers for the operating environment architecture common among PowerPC processors and

describes the programming model. It also describes differences in how the registers are used in the

601 and describes the additional registers that are unique to the 601.

•

Instruction set and addressing modes—Section 3.3, “Instruction Set and Addressing Modes,”

describes the PowerPC instruction set and addressing modes for the PowerPC operating

environment architecture. It defines the PowerPC instructions implemented in the 601 as well as

additional instructions implemented in the 601 but not defined in the PowerPC architecture.

Freescale Semiconductor, Inc.

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