PowerPC 601 RISC Microprocessor Technical Summary

7

The instruction unit generates all instruction addresses; these addresses are both for sequential instruction

fetches and addresses that correspond to a change of program flow. The integer unit generates addresses for

data accesses (both for memory and the I/O controller interface).

After an address is generated, the upper order bits of the logical (effective) address are translated by the

MMU into physical address bits. Simultaneously, the lower order address bits (that are untranslated and

therefore considered both logical and physical), are directed to the on-chip cache where they form the index

into the eight-way set-associative tag array. After translating the address, the MMU passes the higher-order

bits of the physical address to the cache, and the cache lookup completes. For cache-inhibited accesses or

accesses that miss in the cache, the untranslated lower order address bits are concatenated with the translated

higher-order address bits; the resulting 32-bit physical address is then used by the memory unit and the

system interface, which accesses external memory.

The MMU also directs the address translation and enforces the protection hierarchy programmed by the

operating system in relation to the supervisor/user privilege level of the access and in relation to whether the

access is a load or store.

For instruction accesses, the MMU first performs a lookup in the four entries of the ITLB for both block-

and page-based physical address translation. Instruction accesses that miss in the ITLB and all data accesses

cause a lookup in the UTLB and BAT array for the physical address translation. In most cases, the physical

address translation resides in one of the TLBs and the physical address bits are readily available to the on-

chip cache. In the case where the physical address translation misses in the TLBs, the 601 automatically

performs a search of the translation tables in memory using the information in the table search description

register 1 (SDR1) and the corresponding segment register.

Memory management in the 601 is described in more detail in Section 3.6.2, “PowerPC 601 Microprocessor

Memory Management.”

1.6 Cache Unit

The PowerPC 601 microprocessor contains a 32-Kbyte, eight-way set associative, unified (instruction and

data) cache. The cache line size is 64 bytes, divided into two eight-word sectors, each of which can be

snooped, loaded, cast-out, or invalidated independently. The cache is designed to adhere to a write-back

policy, but the 601 allows control of cacheability, write policy, and memory coherency at the page and block

level. The cache uses a least recently used (LRU) replacement policy.

As shown in Figure 1, the cache provides an eight-word interface to the instruction fetcher and load/store

unit. The surrounding logic selects, organizes, and forwards the requested information to the requesting unit.

Write operations to the cache can be performed on a byte basis, and a complete read-modify-write operation

to the cache can occur in each cycle.

The instruction unit provides the cache with the address of the next instruction to be fetched. In the case of

a cache hit, the cache returns the instruction and as many of the instructions following it as can be placed in

the eight-word instruction queue up to the cache sector boundary. If the queue is empty, as many as eight

words (an entire sector) can be loaded into the queue in parallel.

The cache tag directory has one address port dedicated to instruction fetch and load/store accesses and one

dedicated to snooping transactions on the system interface. Therefore, snooping does not require additional

clock cycles unless a snoop hit that requires a cache status update occurs.

Freescale Semiconductor, Inc.

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