PowerPC 601 RISC Microprocessor Technical Summary

9

If a load or store misses in the cache, the operation is managed by the memory unit which prioritizes

accesses to the system bus. Read requests, such as loads, RWITMs, and instruction fetches have priority

over single-beat write operations. The 601 ensures memory consistency by comparing target addresses and

prohibiting instructions from completing out of order if an address matches. Load and store operations can

be forced to execute in strict program order.

The 601 ensures memory consistency by comparing target addresses and prohibiting instructions from

completing out of order if an address matches. Load and store operations can be forced to execute in strict

program order.

1.8 System Interface

Because the cache on the 601 is an on-chip, write-back primary cache, the predominant type of transaction

for most applications is burst-read memory operations, followed by burst-write memory operations, I/O

controller interface operations, and single-beat (noncacheable or write-through) memory read and write

operations. Additionally, there can be address-only operations, variants of the burst and single-beat

operations (global memory operations that are snooped, and atomic memory operations, for example), and

address retry activity (for example, when a snooped read access hits a modified line in the cache).

Memory accesses can occur in single-beat (1–8 bytes) and four-beat burst (32 bytes) data transfers. The

address and data buses are independent for memory accesses to support pipelining and split transactions.

The 601 can pipeline as many as two transactions and has limited support for out-of-order split-bus

transactions.

Access to the system interface is granted through an external arbitration mechanism that allows devices to

compete for bus mastership. This arbitration mechanism is flexible, allowing the 601 to be integrated into

systems that implement various fairness and bus parking procedures to avoid arbitration overhead.

Additional multiprocessor support is provided through coherency mechanisms that provide snooping,

external control of the on-chip cache and TLB, and support for a secondary cache. Multiprocessor software

support is provided through the use of atomic memory operations.

Typically, memory accesses are weakly ordered—sequences of operations, including load/store string and

multiple instructions, do not necessarily complete in the order they begin—maximizing the efficiency of the

bus without sacrificing coherency of the data. The 601 allows read operations to precede store operations

(except when a dependency exists, of course). In addition, the 601 can be configured to reorder high priority

write operations ahead of lower priority store operations. Because the processor can dynamically optimize

run-time ordering of load/store traffic, overall performance is improved.

Freescale Semiconductor, Inc.

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