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PowerPC 601 RISC Microprocessor Technical Summary

Most integer instructions require one clock cycle per stage. Because results for most integer instructions are

available at the end of the execute stage, a series of single-cycle integer instructions allow a throughput of

one instruction per clock cycle. Other instructions, such as the integer multiply, require more than one clock

cycle to complete execution. These instructions reduce the throughput accordingly.

The floating-point pipeline has more stages than the IU pipeline, as shown in Figure 5. The 601 supports

both single- and double-precision floating-point operations, but double-precision instructions generally take

longer to execute, typically by requiring two cycles in the FD, FPM, and FPA stages. However, many of

these instructions, such as the double-precision floating-point multiply (fmul) and double-precision

floating-point accumulate instructions (fmadd, fmsub, fnmadd, and fnmsub), allow stages to overlap. For

example, when the second cycle of the FD stage begins, the first stage of FPM begins. Similarly the FPM

stage overlaps with the FPA stage, allowing these instructions to complete these stages in four clock cycles

instead of six.

Because the PowerPC architecture can be applied to such a wide variety of implementations, instruction

timing among various PowerPC processors varies accordingly.

3.8 System Interface

The system interface is specific for each PowerPC processor implementation.

The 601 provides a versatile system interface that allows for a wide range of implementations. The interface

includes a 32-bit address bus, a 64-bit data bus, and 52 control and information signals (see Figure 6). The

system interface allows for address-only transactions as well as address and data transactions. The 601

control and information signals include the address arbitration, address start, address transfer, transfer

attribute, address termination, data arbitration, data transfer, data termination, and processor state signals.

Test and control signals provide diagnostics for selected internal circuitry.

Figure 6. System Interface

The system interface supports bus pipelining, which allows the address tenure of one transaction to overlap

the data tenure of another. The extent of the pipelining depends on external arbitration and control circuitry.

Similarly, the 601 supports split-bus transactions for systems with multiple potential bus masters—one

device can have mastership of the address bus while another has mastership of the data bus. Allowing

multiple bus transactions to occur simultaneously increases the available bus bandwidth for other activity

and as a result, improves performance.

601

Processor

ADDRESS

ADDRESS ARBITRATION

ADDRESS START

ADDRESS TRANSFER

TRANSFER ATTRIBUTE

ADDRESS TERMINATION

CLOCKS

DATA

DATA ARBITRATION

DATA TRANSFER

DATA TERMINATION

PROCESSOR STATE

TEST AND CONTROL

+3.6 V

Freescale Semiconductor, Inc.

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Go to: www.freescale.com

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