PowerPC 601 RISC Microprocessor Technical Summary

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1.3 Instruction Unit

As shown in Figure 1, the 601 instruction unit, which contains an instruction queue and the BPU, provides

centralized control of instruction flow to the execution units. The instruction unit determines the address of

the next instruction to be fetched based on information from a sequential fetcher and the BPU. The IU also

enforces pipeline interlocks and controls feed-forwarding.

The sequential fetcher contains a dedicated adder that computes the address of the next sequential

instruction based on the address of the last fetch and the number of words accepted into the queue. The BPU

searches the bottom half of the instruction queue for a branch instruction and uses static branch prediction

on unresolved conditional branches to allow the instruction fetch unit to fetch instructions from a predicted

target instruction stream while a conditional branch is evaluated. The BPU also folds out branch instructions

for unconditional branches.

Instructions issued beyond a predicted branch do not complete execution until the branch is resolved,

preserving the programming model of sequential execution. If any of these instructions are to be executed

in the BPU, they are decoded but not issued. FPU and IU instructions are issued and allowed to complete

up to the register write-back stage. Write-back is performed when a correctly predicted branch is resolved,

and instruction execution continues without interruption along the predicted path.

If branch prediction is incorrect, the instruction fetcher flushes all predicted path instructions and

instructions are issued from the correct path.

1.3.1 Instruction Queue

The instruction queue, shown in Figure 1, holds as many as eight instructions (a cache block) and can be

filled from the cache during a single cycle. The instruction fetch can access only one cache sector at a time

and will load as many instruction as space in the IQ allows.

The upper half of the instruction queue (Q4–Q7) provides buffering to reduce the frequency of cache

accesses. Integer and branch instructions are dispatched to their respective execution units from Q0 through

Q3. Q0 functions as the initial decode stage for the IU.

For a more detailed overview of instruction dispatch, see Section 3.7, “Instruction Timing.”

1.4 Independent Execution Units

The PowerPC architecture’s support for independent floating-point, integer, and branch processing

execution units allows implementation of processors with out-of-order instruction issue. For example,

because branch instructions do not depend on GPRs or FPRs, branches can often be resolved early,

eliminating stalls caused by taken branches.

The following sections describe the 601’s three execution units—the BPU, IU, and FPU.

1.4.1 Branch Processing Unit (BPU)

The BPU performs condition register (CR) look-ahead operations on conditional branches. The BPU looks

through the bottom half of the instruction queue for a conditional branch instruction and attempts to resolve

it early, achieving the effect of a zero-cycle branch in many cases.

The BPU uses a bit in the instruction encoding to predict the direction of the conditional branch. Therefore,

when an unresolved conditional branch instruction is encountered, the 601 fetches instructions from the

predicted target stream until the conditional branch is resolved.

Freescale Semiconductor, Inc.

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