8

PowerPC 601 RISC Microprocessor Technical Summary

1.7 Memory Unit

The 601’s memory unit contains read and write queues that buffer operations between the external interface

and the cache. These operations are comprised of operations resulting from load and store instructions that

are cache misses and read and write operations required to maintain cache coherency, table search, and other

operations. The memory unit also handles address-only operations and cache-inhibited loads and stores. As

shown in Figure 2, the read queue contains two elements and the write queue contains three elements. Each

element of the write queue can contain as many as eight words (one sector) of data. One element of the write

queue, marked snoop in Figure 2, is dedicated to writing cache sectors to system memory after a modified

sector is hit by a snoop from another processor or snooping device on the system bus. The use of the write

queue guarantees a high priority operation that ensures a deterministic response behavior when snooping

hits a modified sector.

Figure 2. Memory Unit

The other two elements in the write queue are used for store operations and writing back modified sectors

that have been deallocated by updating the queue; that is, when a cache location is full, the least-recently

used cache sector is deallocated by first being copied into the write queue and from there to system memory.

Note that snooping can occur after a sector has been pushed out into the write queue and before the data has

been written to system memory. Therefore, to maintain a coherent memory, the write queue elements are

compared to snooped addresses in the same way as the cache tags. If a snoop hits a write queue element, the

data is first stored in system memory before it can be loaded into the cache of the snooping bus master.

Coherency checking between the cache and the write queue prevents dependency conflicts. Single-beat

writes in the write queue are not snooped; coherency is ensured through the use of special cache operations

that accompany the single-beat write operation on the bus.

Execution of a load or store instruction is considered complete when the associated address translation

completes, guaranteeing that the instruction has completed to the point where it is known that it will not

generate an internal exception. However, after address translation is complete, a read or write operation can

still generate an external exception.

Load and store instructions are always issued and translated in program order with respect to other load and

store instructions. However, a load or store operation that hits in the cache can complete ahead of those that

miss in the cache; additionally, loads and stores that miss the cache can be reordered as they arbitrate for the

system bus.

READ

QUEUE

WRITE QUEUE

SNOOP

ADDRESS

DATA

ADDRESS

(from cache)

DATA

(from cache)

SYSTEM INTERFACE

(to cache)

DATA QUEUE

(four word)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

AR

CH

IVE

D B

Y F

RE

ES

CA

LE

SE

MI

CO

ND

UC

TO

R,

INC

.